Memory and system architecture for 400Gb/s networking and beyond

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 116-117

  Maheshwari, Dinesh ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC RANDOM ACCESS STORAGE;

COMPUTING SYSTEM; LINE CARD; MEMORY SYSTEMS; PACKET RATE; SYSTEM ARCHITECTURES; TRANSACTION RATES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84898071475     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757362     Document Type: Conference Paper

References (6)

1. Cypress Semiconductor QDR-II+ datasheet, Updated 11/05/2012.
2. Cypress Semiconductor QDR-IV datasheet, Updated 11/15/2013.
3. J. D'Ambrosia, "Ethernet's Next Step: 400 Gigabit Ethernet", Ethernet Technology Summit 2013.
4. D. Yu, "Innovative Wafer-based Interconnect Enabling System Integration and Semiconductor Paradigm Shifts", IEEE International Interconnect Technology Conference2013, pp. 1-3
5. J. Sun, "System Scaling and Collaborative Open Innovation", Symposium on VLSI Technology,2013, pages T2-T7.
6. C. Hou, "3DIC Integration: A Foundry Perspective", International Conference on Electronics Packaging2012. Keynote Speech.