Loopback architecture for wafer-level at-speed testing of embedded HyperTransport™ processor links

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 605-608

  Loke, Alvin L S ^a   Doyle, Bruce A ^a   Oshima, Michael M ^a   Williams, Wade L ^a   Lewis, Robert G ^a   Wang, Charles L ^a   Hanpachern, Audie ^a   Tucker, Karen M ^a   Gurunath, Prashanth ^a   Asada, Gladney C ^a   Lackey, Chad O ^a   Wee, Tin Tin ^a   Fang, Emerson S ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AT-SPEED TESTING; CMOS WAFERS; HYPERTRANSPORT; PRODUCTION SCREENING; WAFER LEVEL;

COMPUTER ARCHITECTURE; INTEGRATED CIRCUITS; SILICON WAFERS;

DIES;

EID: 74049146740     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280778     Document Type: Conference Paper

References (5)

1. http://www.hypertransport.org/
2. S. Narasimha et al., "High-performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography," IEEE Int. Electron Devices Meeting, Dec. 2006.
3. W. L. Williams et al., "Low latency clock domain transfer for simultaneously mesochronous, plesiochronous, and heterochronous interfaces," IEEE Int. Symp. Asynchronous Circuits and Systems, Mar. 2007.
4. E. Fang et al., "A 5.2Gbps HyperTransport" integrated AC coupled receiver with DFR DC restore," IEEE Symp. VLSI Circuits, Jun. 2007.
5. G.-Y. Wei et al., "A variable-frequency parallel I/O interface with adaptive power-supply regulation," IEEE J. Solid-State Circuits, Nov. 2000.