A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 96-108

  Ohbayashi, Shigeki ^a   Yabuuchi, Makoto ^a   Kono, Kazushi ^a   Oda, Yuji ^b   Imaoka, Susumu ^c   Usui, Keiichi ^d   Yonezu, Toshiaki ^a   Iwamoto, Takeshi ^a   Nii, Koji ^a   Tsukamoto, Yasumasa ^a   Arakawa, Masashi ^a   Uchida, Takahiro ^a   Okada, Masakazu ^a   Ishii, Atsushi ^a   Yoshihara, Tsutomu ^e   Makino, Hiroshi ^a   Ishibashi, Koichiro ^a   Shinohara, Hirofumi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Shikino High Tech Corporation   (Japan)

^c Renesas Design Corporation   (Japan)

^d Daioh Electric Corp   (Japan)

^e WASEDA UNIVERSITY   (Japan)

Author keywords

65 nm CMOS; 6T SRAM; CMOS; embedded SRAM; fuse; known good die (KGD); redundancy; SRAM; wafer level burn in

Indexed keywords

EID: 85008019201     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908004     Document Type: Article

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