A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 434-435

  Takaya, Satoshi ^a   Nagata, Makoto ^a   Sakai, Atsushi ^b   Kariya, Takashi ^b   Uchiyama, Shiro ^b   Kobayashi, Harufumi ^b   Ikeda, Hiroaki ^b  

^a KOBE UNIVERSITY   (Japan)

^b ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT TECHNIQUES; ELECTRICAL AND MECHANICAL PROPERTIES; LOW-POWER CONSUMPTION; MOBILE APPLICATIONS; PERFORMANCE VARIATIONS; SILICON INTERPOSERS; THROUGH SILICON VIAS; VERTICAL COMMUNICATIONS;

DIGITAL CONTROL SYSTEMS; MECHANICAL PROPERTIES; MICROPROCESSOR CHIPS; SILICON;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84876562050     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487803     Document Type: Conference Paper

References (6)

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2. J. Roullard, et al., "Evaluation of 3D Interconnect Routing and Stacking Strategy to Optimize High Speed Signal Transmission for Memory on Logic," in IEEE Electronic Components and Technology Conf., pp. 8-13, 2012
3. J. Jeddeloh and B. Keeth, "Hybrid Memory Cube New DRAM Architecture Increases Density and Performance," IEEE Symp. VLSI Circuits, pp. 87-88, 2012
4. H. Takatani, et al., "PDN Impedance and Noise Simulation of 3D SiP with a Widebus Structure," IEEE Electronic Components and Technology Conf., pp. 673-677, 2012
5. T. Hashida and M. Nagata, "An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 789-796, 2011
6. Y. Liu, et al., "A Compact Low-Power 3D I/O in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 142-143, 2012