An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 121-131

  Bae, Seung Jun ^a   Park, Kwang Il ^a   Ihm, Jeong Don ^a   Song, Ho Young ^a   Lee, Woo Jin ^a   Kim, Hyun Jin ^a   Kim, Kyoung Ho ^a   Park, Yoon Sik ^a   Park, Min Sang ^a   Lee, Hong Kyong ^a   Bang, Sam Young ^a   Moon, Gil Shin ^a   Hwang, Seok Won ^a   Cho, Young Chul ^a   Hwang, Sang Jun ^a   Kim, Dae Hyun ^a   Lim, Ji Hoon ^a   Kim, Jae Sung ^a   Kim, Sung Hoon ^a   Jang, Seong Jin ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   Kim, Kinam ^a   Cho, Soo In ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

Analog majority voter; data bus inversion; duty cycle corrector; graphics DRAM; single ended signaling; Vref calibration

Indexed keywords

EID: 85008049440     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2007.908002     Document Type: Article

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