A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 44-45

  Bae, Yong Cheol ^a   Park, Joon Young ^a   Rhee, Sang Jae ^a   Ko, Seung Bum ^a   Jeong, Yonggwon ^a   Noh, Kwang Sook ^a   Son, Younghoon ^a   Youn, Jaeyoun ^a   Chu, Yonggyu ^a   Cho, Hyunyoon ^a   Kim, Mijo ^a   Yim, Daesik ^a   Kim, Hyo Chang ^a   Jung, Sang Hoon ^a   Choi, Hye In ^a   Yim, Sungmin ^a   Lee, Jung Bae ^a   Choi, Joo Sun ^a   Oh, Kyungseok ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BACKWARD COMPATIBLE; CHANNEL BANDWIDTH; CONTROL SCHEMES; DATA BANDWIDTH; HIGH QUALITY; LOW POWER; MOBILE DRAM; PORTABLE DEVICE; POWER BUDGETS; POWER EFFICIENCY; SERIAL I/O; TABLET PCS;

BANDWIDTH; CALIBRATION; MOBILE DEVICES; MOBILE TELECOMMUNICATION SYSTEMS; PERSONAL COMPUTERS;

MICROPROCESSOR CHIPS;

EID: 84860695878     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176871     Document Type: Conference Paper

References (4)

1. J. Kim, et al. "A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4 128 I/Os using TSV based Stacking," ISSCC Dig. Tech. Papers, pp. 496-497, Feb. 2011.
2. H. Werkmann, et al. "GDDR5 Training - Challenges and Solutions for ATE-Based Test," Asian Test Symposium, pp. 423-428, 2008.
3. JEDEC Standard DDR3 SDRAM Specification, JESD79-3E, July 2010.
4. H. Song, et al. "A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die-Termination,"ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2003.