A compact low-power 3D I/O in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 142-143

  Liu, Yong ^a   Luk, Wing ^a   Friedman, Daniel ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D INTERCONNECT; DATA BANDWIDTH; GATED DIODES; INTER-CHIP; LOW POWER; LOW SWING; POWER EFFICIENCY; POWER REDUCTIONS; SIGNAL INTEGRITY; SILICON INTEGRATION; THROUGH-SILICON-VIA; ULTRA-HIGH BANDWIDTH;

LOADING;

THREE DIMENSIONAL;

EID: 84860680846     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176900     Document Type: Conference Paper

References (6)

1. M. Farooq et al., "3D copper TSV integration, testing and reliability," IEEE IEDM, pp. 143-146, Dec. 2011.
2. F. O'Mahony et al., "A 47x10 Gb/s 1.4 mW/Gb/s parallel interface in 45nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2828-2837, Dec. 2010.
3. T. Dickson et al., "An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects," IEEE Symp. VLSI Circuits, pp. 80-81, June 2011.
4. W. Luk et al., "Gated-diode amplifiers," IEEE Trans. Circ. Sys. II, pp. 226-270, May 2005.
5. W. Luk et al., "Gated Diode Memory Cells," U.S. Patent Application US 20050128803A1, Dec. 2003; IBM Disclosure YOR820020472, Sept. 2002.
6. S. Ranganathan et al., "Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003.