Use of MISRs for compression and diagnostics

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 735-743

  Keller, Brion ^a   Bartenstein, Thomas ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA VOLUME; RESPONSE COMPRESSION;

DATA COMPRESSION; DATA STRUCTURES; PROGRAM DIAGNOSTICS; RESPONSE TIME (COMPUTER SYSTEMS);

COMPUTER SYSTEM RECOVERY;

EID: 33847131366     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584036     Document Type: Conference Paper

References (10)

1. P.H. Bardell and W.H. McAnney, "Self-Testing of Multi-chip Logic Modules," Proc. International Test Conference, pp. 200-204, 1982.
2. C. Barnhart et al, "Extending OPMISR beyond 10X Scan Test Efficiency", IEEE Design &Test of Computers Sept - Oct 2002.
3. J. Rajski et al, "Embedded Deterministic Test for Low Cost Manufacturing Test," Proc. International Test Conference, pp. 301-310, 2002.
4. D. M. Wu et al, "H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing," Proc. International Test Conference, pp. 1229-1238, 2003.
5. W.H. McAnney and J. Savir, "There is Information in Faulty Signatures," Proc. International Test Conference, pp. 630-636, 1987.
6. C. Barnhart et al, "OPMISR: The Foundation for Compressed ATPG Vectors," Proc. International Test Conference, pp. 748-757, 2001.
7. P. Song, F. Motika, D. Knebel, R. Rizzolo, M. Kusko, J. Lee, M. McManus, "Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor," Proc. International Test Conference, pp. 1073-1082, 1999.
8. S. Mitra and K.S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Proc. International Test Conference, pp. 311-320, 2002.
9. G. Mrugalski, A. Pogiel, J. Rajski, J. Tyszer and Chen Wang, "Fault Diagnosis in Designs with Convolutional Compactors," Proc. International Test Conference, pp. 498-507, 2004.
10. V. Chickermane, B. Foutz and B. Keller, "Channel Masking Synthesis for Efficient On-Chip Test Compression," Proc. International Test Conference, pp. 452-461, 2004.