Capturing the sensitivity of optical network quality metrics to its network interface parameters

Concurrency and Computation: Practice and Experience

Volumn 26, Issue 15, 2014, Pages 2504-2517

  Ortiń Obón, Marta ^a   Ramini, Luca ^b   Viñals, Víctor ^a   Bertozzi, Davide ^b  

^a UNIVERSITY OF ZARAGOZA   (Spain)

^b UNIVERSITY OF FERRARA   (Italy)

Author keywords

Interconnection networks; Network interface; Silicon photonics

Indexed keywords

BINARY ALLOYS; CESIUM ALLOYS; COMPLEX NETWORKS; ENERGY UTILIZATION; FIBER OPTIC NETWORKS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); INTERFACES (COMPUTER); NETWORK-ON-CHIP; OPTICAL COMMUNICATION; SILICON COMPOUNDS; SILICON PHOTONICS;

BANDWIDTH SCALABILITY; BUFFERING STRATEGY; EVALUATION METHODOLOGIES; INTERFACE PARAMETERS; MULTI CORE AND MANY CORES; NETWORK INTERFACE ARCHITECTURE; OPTICAL NETWORKS ON CHIPS; REGISTER TRANSFER LEVEL;

NETWORK ARCHITECTURE;

EID: 84907692987     PISSN: 15320626     EISSN: 15320634     Source Type: Journal    
DOI: 10.1002/cpe.3330     Document Type: Conference Paper

References (34)

1. Koka P, McCracken MO, Schwetman H, Zheng X, Ho R, Krishnamoorthy AV. Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA '10, ACM, New York, NY, USA, 2010; 117-128. DOI: 10.1145/1815961.1815977.
2. Arakawa Y, Nakamura T, Urino Y, Fujita T. Silicon photonics for next generation system integration platform. IEEE Communications Magazine 2013March; 51(3):72-77. DOI: 10.1109/MCOM.2013.6476868.
3. Galland C, Novack A, Liu Y, Ding R, Gould M, Baehr-Jones T, Li Q, Yang Y, Ma Y, Zhang Y, Padmaraju K, Bergmen K, Lim AE-J, Lo G-Q, Hochberg M. A CMOS-compatible silicon photonic platform for high-speed integrated opto-electronics. Proceedings of Integrated Photonics: Materials, Devices, and Applications, Grenoble, France, 2013; 87670G.
4. Kapur P, Saraswat KC. Optical interconnects for future high performance integrated circuits. Physica E: Lowdimensional Systems and Nanostructures 2003; 16:620 -627. DOI: 10.1016/S1386-9477(02)00686-0. (Available from: http://www.sciencedirect.com/science/article/pii/S1386947702006860, Accessed on 26 June 2014).
5. Koohi S, Abdollahi M, Hessabi S. All-optical wavelength-routed NoC based on a novel hierarchical topology. International Symposium on Networks on Chip (NoCS), Pittsburgh, PA, 2011; 97-104.
6. Chan J, Hendry G, Biberman A, Bergman K. Architectural design exploration of chip-scale photonic interconnection networks using physical-layer analysis. 2010 Conference on (OFC/NFOEC) Optical Fiber Communication (OFC), Collocated National Fiber Optic Engineers Conference, San Diego, CA, USA, 2010; 1-3.
7. Batten C, Joshi A, Stojanovic V, Asanovic K. Designing chip-level nanophotonic interconnection networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2012; 2:137-153. DOI: 10.1109/JETCAS.2012.2193932.
8. Kapoor R, Porter G, Tewari M, Voelker GM, Vahdat A. Chronos: predictable low latency for data center applications. Procs of the Third ACM Symposium on Cloud Comp., ACM, New York, NY, USA, 2012; 9:1-9:14. DOI: 10.1145/2391229.2391238.
9. Hendry G, Chan J, Kamil S, Oliker L, Shalf J, Carloni LP, Bergman K. Silicon nanophotonic network-on-chip using TDM arbitration. Annual Symposium on High Performance Interconnects (HOTI), Mountain View, CA, 2010;88-95. DOI: 10.1109/HOTI.2010.12.
10. Beamer S, Sun C, Kwon Y-J, Joshi A, Batten C, Stojanovic V, Asanovic K. Re-architecting dram memory systems with monolithically integrated silicon photonics. ISCA, ACM, New York, NY, USA, 2010; 129-140. (Available from: http://dblp.uni-trier.de/db/conf/isca/isca2010.html#BeamerSKJBSA10, Accessed on 26 June 2014).
11. Pan Y, Kumar P, Kim J, Memik G, Zhang Y, Choudhary A. Firefly: illuminating future network-on-chip with nanophotonics. Proceedings of the International Symposium on Computer Architecture, ISCA '09, ACM, New York, NY, USA, 2009; 429-440. DOI: 10.1145/1555754.1555808.
12. Vantrease D, Binkert N, Schreiber R, Lipasti MH. Light speed arbitration and flow control for nanophotonic interconnects. 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009. Micro-42, New York, NY, 2009; 304-315.
13. Joshi A, Batten C, Kwon Y-J, Beamer S, Shamim I, Asanovic K, Stojanovic V. Silicon-photonic clos networks for global on-chip communication. International Symposium on Networks-on-Chip, San Diego, CA, 2009; 124-133.
14. Pan Y, Kim J, Memik G. Flexishare: channel sharing for an energy-efficient nanophotonic crossbar. International Symposium on High Performance Computer Architecture, Bangalore, 2010; 1-12.
15. Morris R, Kodi AK, Louri A. Dynamic reconfiguration of 3d photonic networks-on-chip for maximizing performance and improving fault tolerance. Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-45, IEEE Computer Society, Washington, DC, USA, 2012; 282-293. DOI:10.1109/MICRO.2012.34.
16. Bartolini S, Grani P. Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. Proceedings of the First International Workshop on Many-Core Embedded Systems, MES '13, ACM, New York, NY, USA, 2013; 9-16. DOI: 10.1145/2489068.2489070.
17. Koka P, McCracken MO, Schwetman H, Chen CHO, Zheng X, Ho R, Raj K, Krishnamoorthy AV. A microarchitectural analysis of switched photonic multi-chip interconnects. Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA '12, IEEE Computer Society, Washington, DC, USA, 2012; 153-164. (Available from: http://dl.acm.org/citation.cfm?id=2337159.2337177, Accessed on 26 June 2014).
18. Kurian G, Sun C, Chen CHO, Miller JE, Michel J, Wei L, Antoniadis DA, Peh LS, Kimerling L, Stojanovic V, Agarwal A. Cross-layer energy and performance evaluation of a nanophotonic manycore processor system using real application workloads. International Parallel Distributed Processing Symposium (IPDPS), Shanghai, 2012; 1117-1130. DOI: 10.1109/IPDPS.2012.103.
19. Ramini L, Grani P, Bartolini S, Bertozzi D. Contrasting wavelength-routed optical NoC topologies for power-efficient 3d-stacked multicore processors using physical-layer analysis. Proceedings of the Conference on Design, Automation and Test in Europe, DATE '13, EDA Consortium, San Jose, CA, USA, 2013; 1589-1594. (Available from: http://dl. acm.org/citation.cfm?id=2485288.2485666, Accessed on 26 June 2014).
20. Bahirat S, Pasricha S. Meteor: hybrid photonic ring-mesh network-on-chip for multicore architectures. ACM Transactions on Embedded Computing Systems March 2014; 13(3s):116:1-116:33. DOI: 10.1145/2567940.
21. Chan J, Hendry G, Biberman A, Bergman K. Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis. Journal of Lightwave Technology 2010; 28:1305-1315. DOI: 10.1109/JLT.2010.2044231.
22. O'Connor I, Van Thourhout D, Scandurra A. Wavelength division multiplexed photonic layer on CMOS. Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, INA-OCMC '12, ACM, New York, NY, USA, 2012; 33-36. DOI: 10.1145/2107763.2107772.
23. Biere M, Gheorghe L, Nicolescu G, O'Connor I, Wainer G. Towards the high-level design of optical networks-on- chip. Formalization of opto-electrical interfaces. International Conference on Electronics, Circuits and Systems, Marrakech, 2007; 427-430. DOI: 10.1109/ICECS.2007.4511021.
24. O'Connor I, Brière M, Drouard E, Kazmierczak A, Tissafi-Drissi F, Navarro D, Mieyeville F, Dambre J, Stroobandt D, Fedeli J-M, Lisik Z, Gaffiot F. Towards reconfigurable optical networks-on-chip. RECO SoC, Montpellier, France, 2005; 121-128.
25. Le Beux S, Trajkovic J, O'Connor I, Nicolescu G, Bois G, Paulin P. Optical ring network-on-chip (ORNoC): architecture and design methodology. Design, Automation Test in Europe Conference Exhibition (DATE), Grenoble, France, 2011; 1-6. DOI: 10.1109/DATE.2011.5763134.
26. Dally W, Towles B. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc.: San Francisco, CA, USA, 2003.
27. Hansson A, Goossens K, Rdulescu A. Avoiding message-dependent deadlock in network-based systems on chip. VLSI Design 2007; 2007:Article ID 95859, 10 pages.
28. TileraCorporation. Tile-Gx8016 specification. (Available from: http://www.tilera.com/sites/default/files/productbriefs/ Tile-Gx-8016-SB011-03.pdf, Accessed on 26 June 2014).
29. Strano A, Ludovici D, Bertozzi D. A library of dual-clock FIFOs for cost-effective and flexibleMPSoC design. International Conference on Embedded Computer Systems (SAMOS), Samos, 2010; 20-27. DOI: 10.1109/ICSAMOS.2010.5642098.
30. Leu J, Stojanovic V. Injection-locked clock receiver for monolithic optical link in 45nm SOI. 2011 IEEE Asian Solid State Circuits Conference (A-SSCC), Jeju, 2011; 149-152. DOI: 10.1109/ASSCC.2011.6123624.
31. Stergiou S, Angiolini F, Carta S, Raffo L, Bertozzi D, De Micheli G. xpipes Lite: a synthesis oriented design library for networks on chips. Design, Automation and Test in Europe, Vol. 2, Munich, Germany, 2005; 1188-1193.doi:10.1109/DATE.2005.1.
32. Gilabert F, Gomez ME, Medardoni S, Bertozzi D. Improved utilization of NoC channel bandwidth by switch replication for cost-effective multi-processor systems-on-chip. International Symposium on Networks-on-Chip (NOCS), Grenoble, France, 2010; 165-172. DOI: 10.1109/NOCS.2010.25.
33. Grotker T, Liao S, Martin G, Swan S. System Design with SystemC. Kluwer Academic Publishers: Hinghman, MA, USA, 2002.
34. Chan J, Hendry G, Biberman A, Bergman K, Carloni LP. PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks. Proceedings of the Conference on Design, Automation and Test in Europe, DATE '10, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, 2010; 691-696. (Available from: http://dl.acm.org/citation.cfm?id=1870926.1871093, Accessed on 26 June 2014).