A micro-architectural analysis of switched photonic multi-chip interconnects

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 153-164

  Koka, Pranay ^a   McCracken, Michael O ^a   Schwetman, Herb ^a   Chen, Chia Hsin Owen ^b   Zheng, Xuezhe ^a   Ho, Ron ^a   Raj, Kannan ^a   Krishnamoorthy, Ashok V ^a  

^a ORACLE CORPORATION   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX TOPOLOGY; CONSTRAINED METHOD; ENERGY CHARACTERISTICS; EQUIVALENT BANDWIDTH; MESSAGE PATTERNS; MICRO-ARCHITECTURAL ANALYSIS; MULTI-CHIP; OFF-CHIP; OPTICAL POWER; PHOTONIC INTERCONNECTS; POINT-TO-POINT NETWORK; POWER CHARACTERISTIC; POWER EFFICIENT; REALISTIC DEVICES; SILICON PHOTONICS; SWITCHED NETWORKS; TRAFFIC PATTERN; WAVEGUIDE CROSSINGS;

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; OPTICAL INTERCONNECTS; PHOTONICS; WAVEGUIDES;

SWITCHING CIRCUITS;

EID: 84864830695     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237014     Document Type: Conference Paper

References (45)

1. S. Beamer C. Sun et al., "R e-architecting DR AM memory systems with monolithically integrated silicon photonics," in ISCA, 2010 .
2. J. Chan, G. Hendry et al., "Architectural exploration of chipscale photonic interconnection network designs using physicallayer analysis," J. Lightwave Tech., 2010.
3. D. Vantrease, R. Schreiber et al., "Corona: System implications of emerging nanophotonic technology," in ISCA, 2008.
4. Y. Pan, P. Kumar et al., "Firefly : illuminating future networkon-chip with nanophotonics," in ISCA, 2009.
5. A. Krishnamoorthy, R. Ho et al., "Computer systems based on silicon photonic interconnects," Proc. IEEE, 2009 .
6. P. Koka, M. O. McCracken et al., "Silicon-photonic network architectures for scalable, power-efficient multi-chip systems," in ISCA, 2010.
7. A. Shacham, B. Lee et al., "Photonic NoC for DMA communications in chip multiprocessors," in HOTI, 2007 .
8. AiDi Corp. (2011 ) Fiber array product details. [Online]. Available: http://www.aidicorp.com/
9. H. Rong, Y. Kuo et al., "High efficiency wavelength conversion of 10 gb/s data in silicon waveguides," Opt. Expr., vol. 14, no. 3, 2006.
10. R. Claps, D. Dimitropoulos et al., "Observation of stimulated raman amplification in silicon waveguides," in LEOS, vol. 1. IEEE, 2003, pp. 134-135.
11. E. Dulkeith, Y. Vlasov et al., "Self-phase-modulation in submicron silicon-on-insulator photonic wires," Opt. Expr., 2006.
12. I. Hsieh, X. Chen et al., "Cross-phase modulation in si photonic wire waveguides," in CLEO, 2006.
13. E. Dulkeith, F. Xia et al., "Group index and group velocity dispersion in silicon-on-insulator photonic wires," Opt. Expr., 2006.
14. M. Dinu, F. Quochi et al., "Third-order nonlinearities in silicon at telecom wavelengths," Appl. Phys. Lett, 2003 .
15. W. Dally, B. Towles et al., Principles and Practices of Interconnection Networks. Morgan Kaufman, 2004.
16. H. Liu, H. Tam et al., "Low-loss wavguide crossing using a multimode interference structure," Opt. Comm., 2004.
17. F. Xu, A. Poon et al., "Silicon cross-connect filters using microring resonator coupled multimode-interference-based wavguide crossings," Opt. Expr., 2008.
18. P. Sanchis, P. Villalba et al., "Highly efficient crossing structure for silicon-on-insulator waveguides," Opt. Lett., 2009 .
19. Y. S akamaki, T. S aida et al., "Loss reduction of wavguide crossings by wavefront matching method and their application to integrated optical circuits," J. Q. Elec., 2009.
20. A. Krishnamoorthy, J. Cunningham et al., "Optical proximity communication with passively aligned silicon photonic chips," J. Q. Elec., 2009. 164
21. J. Yao, X. Zheng et al., "Grating-coupler based optical interlayer coupling," in IEEE Group IV Photonics, 2011 .
22. F. Sun, J. Yu et al., "A 2 × 2 optical switch based on plasma dispersion effect in silicon-on-insulator," Opt. Comm., 2006.
23. J. Van Campenhout, W. Green et al., "Low-power, 2 × 2 silicon electro-optic switch with 1 l 0-nm bandwidth for broadband reconfigurable optical networks," Opt. Expr., 2009 .
24. P. Dong, S. Liao et al., "Submilliwatt, ultrafast and broadband electro-optic silicon switches," Opt. Expr., 2010 .
25. P. Dong, S. Preble et al., "All-optical compact silicon comb switch," Opt. Expr., 2007 .
26. Y. Vlasov, W. Green et al., "High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks," Nature Photonics, vol. 2, no. 4, 2008.
27. X. Zheng, F. Liu et al., "Ultra-low power arrayed. cmos silicon, photonic transceivers for an 80 gbps wdm optical link, In National Fiber Optic Engineers Coriference, 2011 .
28. X. Zheng, P. Koka et al., "Silicon photonic WDM point-to-point network for multi-chip processor interconnects," in Group IV Photonics, 2008, pp. 380-382.
29. N. Klrman et al., "Leveraging optical technology in future bus-based chip multiprocessors," in MICRO, 2006.
30. C. B atten, A. Joshi et al., "Building many-core processor-to-dram networks with monolithic cmos silicon photonics," MICRO, vol. 29, no. 4, 2009.
31. G. Loh, "3d-stacked memory architectures for multi-core processors," in ISCA, 2008.
32. F. Petrini, W.-c. Feng et al., "The Quadrics network: highperformance clustering technology," in MICRO, 2002.
33. S. Scott, D. Abts et al., "The blackwidow high-radix Clos network; in ISCA, 2006.
34. K. D. Underwood, K. S. Hemmert et al., "A hardware acceleration unit for MPI queue processing," IPDPS, 2005.
35. T. Sugimoto, N. Komuro et al., "Maximum throughput analysis for rts/cts-used ieee 802. 11 dcf in wireless multi-hop networks," in ICCCE, 2010.
36. R. A. Spanke, V. E. B enes et al., "N-stage planar optical permutation network," Appl. Opt., 1987.
37. P. Dong, W. Qian et al., "Low loss shallow-ridge silicon waveguides," Opt. Express, 2010 .
38. C. Sun, C. - H. O. Chen et al., "DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling," in NOCS, 2012.
39. D. H. Bailey, L. Dagum et al., "NAS parallel benchmark results," in Supercomputing, 1992.
40. M. Geimer, F. Wolf et al., "A scalable tool architecture for diagnosing wait states in massively parallel applications," Parallel Comput., vol. 35, 2009.
41. G. Singh, T. Bhattacharjee et al., "DeSign of non-blocking and rearrangeable modified banyan network WIth electro-optic MZI switching elements," J. WASET, 2008.
42. H. Gu, K. H. Mo et al., "A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip," in ISVLSI, 2009.
43. N. Klrman, J. F. Martinez et al., "A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing," in ASPLOS, 2010.
44. J. Ahn, M. Fiorentino et al., "Devices and architectures for photonic chip-scale integration," Appl. Phys. A, 2009 .
45. N. Binkert, A. Davis et al., "The role of optics in future high radix switch design," in ISCA, 2011.