A library of dual-clock FIFOs for cost-effective and flexible MPSoC design

Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010

Volumn , Issue , 2010, Pages 20-27

  Strano, Alessandro ^a   Ludovici, Daniele ^b   Bertozzi, Davide ^a  

^a UNIVERSITY OF FERRARA   (Italy)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN ISSUES; IMPLEMENTATION COST; IP BLOCK; MULTI PROCESSOR SYSTEM ON CHIPS; NOC ARCHITECTURES; ON-CHIP INTERCONNECTION NETWORK; OPERATING CONDITION; PERFORMANCE REQUIREMENTS; PLUG-AND-PLAY; POWER BUDGETS; RECENT TRENDS; RESOURCE-CONSTRAINED; SWITCHING FABRIC;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CHIP SCALE PACKAGES; CLOCKS; COMPUTER SIMULATION; COST EFFECTIVENESS; COSTS; DESIGN; EMBEDDED SYSTEMS; INTERCONNECTION NETWORKS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; SYNCHRONIZATION; SYSTEMS ANALYSIS;

COMPUTER ARCHITECTURE;

EID: 78650954935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2010.5642098     Document Type: Conference Paper

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