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Volumn , Issue , 2010, Pages
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Architectural design exploration of chip-scale photonic interconnection networks using physical-layer analysis
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Author keywords
[No Author keywords available]
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Indexed keywords
CHIP-SCALE;
SIMULATION ENVIRONMENT;
ARCHITECTURAL DESIGN;
ENGINEERS;
FIBERS;
INTERCONNECTION NETWORKS;
NETWORK PERFORMANCE;
OPTICAL COMMUNICATION;
OPTICAL FIBERS;
RESISTORS;
COMPUTER SIMULATION;
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EID: 77953922283
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (6)
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References (9)
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