Split Timing Mode (STM) - Answer to dual frequency domain testing

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 140-147

  Sivaram, A T ^a  

^a SCHLUMBERGER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CHIP SCALE PACKAGES; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; MICROPROCESSOR CHIPS; TIMING CIRCUITS; VECTORS;

SPLIT TIMING MODE (STM);

INTEGRATED CIRCUIT TESTING;

EID: 0035684211     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)