Very low cost testers: Opportunities and challenges

IEEE Design and Test of Computers

Volumn 18, Issue 5, 2001, Pages 60-69

  Bedsole, Jay ^a,b   Raina, Rajesh ^a   Crouch, Al ^a   Abadir Motorola, Magdy S ^a  

^a MOTOROLA INC   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEM ON A CHIP (SOC);

AUTOMATIC TESTING; BUILT-IN SELF TEST; CHIP SCALE PACKAGES; COST EFFECTIVENESS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; OPTIMIZATION; SEMICONDUCTOR DEVICE TESTING; VLSI CIRCUITS;

DESIGN FOR TESTABILITY;

EID: 0035446489     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.953273     Document Type: Article

References (8)

1. Test and test equipment
2. DFT-focused chip testers: What can they really do?
3. Low-cost testers: Are they really low cost?
4. The need for highly integrated manufacturing test equipment