Fundamental latency trade-off in architecting DRAM caches: Outperforming impractical SRAM-Tags with a simple and practical design

Proceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012

Volumn , Issue , 2012, Pages 235-246

  Qureshi, Moinuddin K ^a   Loh, Gabe H ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

DRAM Cache; Memory Access Predictor; Stacked Memory

Indexed keywords

ASSOCIATIVITY; CACHE ARCHITECTURE; DESIGN DECISIONS; DESIGN TRADEOFF; MEMORY ACCESS; PERFORMANCE IMPROVEMENTS; STACKED MEMORY; STORAGE OVERHEAD;

COMPUTER ARCHITECTURE; DESIGN; DIGITAL STORAGE; DYNAMIC RANDOM ACCESS STORAGE; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 84876531087     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2012.30     Document Type: Conference Paper

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