Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 99-107

  Kim, Changkyu ^a   Burger, Doug ^a,b   Keckler, Stephen W ^a,b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b UT Austin ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SPEECH RECOGNITION; SWITCHING NETWORKS;

NONUNIFORM CACHE ACCESS (NUCA); WIRE-DELAY PROBLEMS;

CACHE MEMORY;

EID: 10744231529     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261393     Document Type: Review

References (11)

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