Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 99-107

  Kim, Changkyu ^a   Burger, Doug ^a,b,c   Keckler, Stephen W ^a,b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b UT Austin ^*  (United States)

^c University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SPEECH RECOGNITION; SWITCHING NETWORKS;

NONUNIFORM CACHE ACCESS (NUCA); WIRE-DELAY PROBLEMS;

CACHE MEMORY;

EID: 10744231529     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261393     Document Type: Review

References (11)

1. J.M. Hill and J. Lachman, "A 900-MHz 2.25-Mbyte Cache with On-Chip CPU Now in SOI/Cu," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2001, pp. 171-177.
2. J. Huh, D. Burger, and S.W. Keckler, "Exploring the Design Space of Future CMPs," Proc. 10th Int'l Conf. Parallel Architectures and Compilation Techniques, IEEE CS Press, 2001, pp. 199-210.
3. V. Agarwal et al., "Clock Rate vs. IPC: The End of the Road for Conventional Microprocessors," Proc. 27th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 2000, pp. 248-259.
4. D. Matzke, "Will Physical Scalability Sabotage Performance Gains?" Computer, vol. 30, no. 9, Sept. 1997, pp. 37-39.
5. P. Shivakumar and N. Jouppi, Cacti 3.0: An Integrated Cache Timing, Power, and Area Model, tech. report, Compaq Computer Corp., Aug. 2001.
6. R. Desikan et al., Sim-Alpha: A Validated Execution-Driven Alpha 21264 Simulator, tech. report TR-01 -23, Dept. of Computer Sciences, Univ. Texas at Austin, 2001.
7. Int'l Technology Roadmap for Semiconductors, Semiconductor Industry Assoc., 2001; http://public.itrs.net/HomeStart.htm.
8. C. Kim, D. Burger, and S.W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-10), ACM Press, 2002, pp. 211-222.
9. R. Kessler et al., "Inexpensive Implementations of Set-Associativity," Proc. 16th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1989, pp. 131-139.
10. E. Hallnor and S. Reinhardt, "A Fully Associative Software-Managed Cache Design," Proc. 27th Int'l Symp. Computer Architecture, IEEE CS Press, 2000, pp. 107-116.
11. H. Pilo et al., "An 833MHz 1.5w 18Mb CMOS SRAM with 1.67Gb/s/pin," Proc. 2000 IEEE Int'l Solid-State Circuits Conf., IEEE Press, 2000, pp. 266-267.