Lincoln Laboratory's 3D Circuit Integration Technology

Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits

Volumn 2, Issue , 2008, Pages 393-411

  Burns, James ^a   Aull, Brian ^a   Berger, Robert ^a   Checka, Nisha ^a   Chen, Chang Lee ^a   Chen, Chenson ^a   Gouker, Pascale ^a   Keast, Craig ^a   Knecht, Jeffrey ^a   Soares, Antonio ^a   Suntharalingam, Vyshnavi ^a   Tyrrell, Brian ^a   Warner, Keith ^a   Wheeler, Bruce ^a   Wyatt, Peter ^a   Yost, Donna ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3D imager; 3D integrated circuit; Through silicon vias (TSVs); Wafer wafer alignment; Wafer wafer bond

Indexed keywords

EID: 84891307630     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9783527623051.ch20     Document Type: Chapter

References (25)

1. Burns, J.A., Aull, B.F., Chen, C.K. et al. (2006) A wafer-scale 3-D circuit integration technology. IEEE Transactions Electron Devices, 53 (10), 2507-2516.
2. McClelland, R.W., Bozler, C.O. and Fan, J.C.C. (1980) TP-A2 the cleft process: A technique for producing many epitaxial single-crystal GaAs films by employing one reusable substrate. IEEE Transactions Electron Devices, 27 (11), 2188.
3. Sailer, P.M., Singhal, P., Hopwood, J. et al. (1997) Creating 3D circuits using transferred films. IEEE Circuits Devices Magazine, 13 (6), 27-30.
4. Burns, J., McIlrath, L., Hopwood, J. et al. (2000) An SOI-based three-dimensional integrated circuit technology. IEEE International SOI Conference Proceeedings, pp. 20-21.
5. Burns, J., McIlrath, L.,Keast, C. et al. (2001) Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip. Digest Tech. Papers IEEE International Solid-State Circuits Conference, 453, pp. 268-269.
6. Reif, R., Fan, A., Chen, K.-N. and Das, S. (2002) Fabrication technologies for threedimensional integrated circuits. Proceedings IEEE International Symposium Quality Electronic Design, pp. 33-37.
7. Chan, V.W.C., Chan, P.C.H. and Chan, M. (2000) Three dimensional CMOS integrated circuits on large grain polysilicon films. Tech. Digest IEEE International Electron Devices Mtg., pp. 161-164.
8. Fukushima, T., Yamada, Y., Kikuchi, H. and Koyanagi, M. (2005) New threedimensional integration technology using self-assembly technique. Tech. Digest IEEE International Electron Devices Mtg., pp. 359-362.
9. Lea, R., Jalowiecki, I., Boughton, D. et al. (1999) A 3-D stacked chip packaging solution for miniaturized massively parallel processing. IEEE Transactions Advanced Packaging, 22 (6), 424-432.
10. Fukushima, T., Yamada, Y., Kikuchi, H. and Koyanagi, M. (2005) New threedimensional integration technology using self-assembly technique. Tech. Digest IEEE International Electron Devices Mtg., pp. 359-362.
11. Topol, A., Tulipe, D., Shi, S. et al. (2005) Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). Tech. Digest IEEE International Electron Devices Mtg., pp. 363-366.
12. MITLL Low-Power FD'OI CMOS Process Design Guide, Revision 2006:7, (2006) Advanced Silicon Technology Group, MIT Lincoln Laboratory, 244 Wood St., Lexington, MA 02420.
13. Warner, K., Chen, C., D'Onofrio, R. et al. (2004) An investigation of wafer-to-wafer alignment tolerances for threedimensional integrated circuit fabrication. IEEE International SOI Conference Proceedings, pp. 71-72.
14. Metra 2100 Process Engineer's Manual, Optical Specialties Inc., (1993).
15. Warner, K., Burns, J., Keast, C. et al. (2002) Low-temperature oxide-bonded threedimensional integrated circuits. IEEE International SOI Conference Proceedings, pp. 123-124.
16. Maszara, W.P., Goetz, G., Caviglia, A. and McKitterick, J.B. (1988) Bonding of silicon wafers for silicon-on-insulator. Journal of Applied Physics, 64 (10), 4943-4950.
17. Chen, C.K., Warner, K., Yost, D.R.W. et al. (2007) Scaling three-dimensional SOI integrated-circuit technology. IEEE International SOI Conference Proceedings, p. 87-88.
18. Knecht, J., Yost, D., Burns, J. et al. (2005) 3D via etch development for 3D circuit integration in FD'OI. IEEE International SOI Conference Proceedings, pp. 104-105.
19. Burns, J.,Warner, K. and Gouker, P. (2001) Characterization of fully depleted SOI transistors after removal of the silicon substrate. IEEE International SOI Conference Proceedings, pp. 113-114.
20. Gouker, P., Burns, J., Wyatt, P. et al. (2003) Substrate removal and BOX thinning effects on total dose response of FD'OI NMOSFET. IEEE Transactions Nuclear Science 50 (6), 1776-1783.
21. Chen, C.L., Chen, C.K., Burns, J.A. et al. (2007) Thermal effects of three dimensional integrated circuits stacks. IEEE International SOI Conference Proceedings, p. 91-92.
22. Aull, B., Burns, J., Chen, C. et al. (2006) Laser radar imager based on threedimensional integration of Geiger-mode avalanche photodiodes with two SOI timing-circuit layers. Digest Tech. Papers IEEE International Solid-State Circuits Conference, pp. 304-305.
23. Aull, B.F., Loomis, A.H., Gregory, J. and Young, D. (1998) Geiger-mode avalanche photodiode arrays integrated with CMOS timing circuits. IEEE Annual Device Research Conference Digest, pp. 58-59.
24. Suntharalingam, V., Berger, R., Burns, J.A. et al. (2005) Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology. Digest Tech. Papers IEEE International Solid-State Circuits Conference, pp. 356-357.
25. Warner, K., Oakley, D.C., Donnelly, J.P. et al. (2006) Layer transfer of FD'OI CMOS to 150 mm InP substrates for mixed-material integration. International Conference Indium Phosphide Related Materials, pp. 226-228.