An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 71-72

  Warner, K ^a   Chen, C ^a   D'Onofrio, R ^a   Keast, C ^a   Poesse, S ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT INTEGRATION TECHNIQUES; DIE-TO-DIE SPACING; INTEGRATED CIRCUIT FABRICATION; WAFER-TO-WAFER ALIGNMENT;

BONDING; CONSTRAINT THEORY; FILM GROWTH; INTEGRATED CIRCUITS; LEAST SQUARES APPROXIMATIONS; PHOTODIODES; REGRESSION ANALYSIS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA; SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE CONTROL; TITANIUM COMPOUNDS;

SILICON WAFERS;

EID: 16244407112     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Burns, et al., ISSCC Digest of Technical Papers, pp. 268-269, Feb. 2001.
2. K. Warner, et al., IEEE Int'l SOI Conference Proceedings, pp. 123-125, Oct. 2002.
3. P. Lindner, et al., IEEE Electronic Components and Technology Conference, May 2002.
4. T. Suga, et al., 11th Int'l Conference on Solid-State Sensors and Actuators, pp. 222-225, June 2001.
5. Metra 2100 Process Engineer's Manual, Optical Specialties Inc., 1993.