Creating 3D circuits using transferred films: The ability to fabricate 3D circuits with virtually unrestricted placement of interconnects

IEEE Circuits and Devices Magazine

Volumn 13, Issue 6, 1997, Pages 27-30

  Sailer, Philip M ^a   Singhal, Piyush ^a   Hopwood, Jeffrey ^a   Kaeli, David R ^a   Zavracky, Paul M ^a   Warner, Keith ^a   Vu, D P ^b  

^a NORTHEASTERN UNIVERSITY   (United States)

^b KOPIN CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOW TEMPERATURE OPERATIONS; MASKS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES; THIN FILM CIRCUITS; WSI CIRCUITS;

THREE DIMENSIONAL CIRCUITS; WAFER TRANSFER PROCESS;

CMOS INTEGRATED CIRCUITS;

EID: 0031276215     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.646556     Document Type: Article

References (14)

1. S. Tantsuno, "Japan's Push into Creative Semiconductor Research: 3-Dimensional IC's," Solid State Technology, 30:29-30, March 1987.
2. Y. Hayashi, S. Wada, K. Kajiyana, K. Oyama, R. Koh, S. Takahasi, and T. Kunio, "Fabrication of Three-Dimensional IC Using Cumulatively Bonded IC (CUBIC) Technology," Symposium on VLSI, 1990.
3. S. Akiyama, S. Ogawa, M. Yoneda, Y. Yshii, and Y. Terui, "Multilayer CMOS Device Fabrication on Laser Recrystallized Silicon Islands," Technical Digest, IEDM, 1983, pp. 352-355.
4. P.M. Zavracky, M.M. Zavracky, J.C.C. Fan, and J.P. Salerno, "Optoelectronic Interconnection for II-V Devices on Silicon," U.S. Patent No. 4,890,895. issued January 2, 1990.
5. B.D. Dingle, M.B. Spitzer, R.W. McClelland, J.C.C. Fan, and P.M. Zavracky, "Monolithic Integration of a Light-Emitting Diode Array and a Silicon Circuit Using Transfer Process," Applied Physics Letters, 62(22), May 1993.
6. Private communication with D.P. Vu.
7. Dong-Mei Li, Interconnect Process for 3-Dimensional IC, Department of Electrical and Computer Engineering, MS Thesis, Northeastern University, Boston, MA, May 1995.
8. M.B. Kleiner, S. Kuhn, and W. Weber, "Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology," Proc. of IEEE Electronics Components and Technology Conference (ECTC), 1995, pp. 645-655.
9. S.A. Kuhn, M.B Kleiner, and W. Weber., "Performance Modeling of the Interconnect Structure of a 2-Dimensionally Integrated RISC-Processor/Cache System," Proc. of IEEE Electronics Components and Technology Conference (ECTC), 1995, pp. 592-599.
10. Philip M. Sailer, YIFAN-A 3-D Microprocessor, MS Thesis, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, August 1997.
11. W.M. Meleis, M. Leeser, P.M. Zavracky, and M.M. Vai, "Architectural Design of a Three Dimensional FPGA," Workshop on Field-Programmable Logic and Applications (FPL), September 1997
12. M. Leeser, W.M. Meleis, M.M. Vai, and P.M. Zavracky, "Rothko: A Three Dimensional FPGA Architecture, It's Fabrication, and Design Tools," Conference on Advanced Research in VLSI (ARVLSI), September 1997.
13. J.K. Ousterhout et al., "Magic Tutorials," Computer Science Division (EECS), University of California, Berkeley, CA.
14. Stephen Strickland, Partitioning and Placement Algorithms for Custom 3D VLSI, MS. Thesis, Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, August 1997.