High Performance Switches and Routers

High Performance Switches and Routers

Volumn , Issue , 2006, Pages 1-613

  Chao, H Jonathan ^a   Liu, Bin ^a  

^a NONE

Author keywords

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EID: 84889275982     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9780470113950     Document Type: Book

References (373)

1. G. Vareille, F. Pitel, and J. F. Marcerou, '3-Tbit/s (300 × 11.6 Gbit/s) transmission over 7380 km using C+L band with 25 GHz channel spacing and NRZ format,' in Proc. Optical Fiber Communication Conference and Exhibit, Anaheim, California, vol. 4, pp. PD22-1-3 (Mar. 2001).
2. R. Ryf et al., '1296-port MEMS transparent optical crossconnect with 2.07 petabit/s switch capacity,' in Proc. Optical Fiber Communication Conference and Exhibit, Anaheim, California, vol. 4, pp. PD28-P1 (Mar. 2001).
3. N. Spring, R. Mahajan, and D.Wetherall, 'Measuring ISP topologies with rocketfuel,' in Proc. ACM SIGCOMM, Pittsburgh, Pennsylvania, pp. 133-145 (Aug. 2002).
4. N. Mckeown, 'A fast switched backplane for a gigabit switched router,' Business Communications Review, vol. 27, no. 12 (Dec. 1997).
5. C. Partridge et al., 'A fifty gigabit per second IP router,' IEEE/ACM Transactions on Networking, vol. 6, no. 3. pp. 237-248 (June 1998).
6. VIT10: 10G transponder and VSC8173/75: physical layer multiplexer/demultiplexer, Vitesse. [Online]. Available at: http://www.vitesse.com
7. CA16: 2.5 Gbit/s DWDM with 16-channel 155 Mb/s multiplexer and demultiplexer and TB64: Uncoded 10 Gbit/s transponder with 16-channel 622 Mbit/s Multiplexer and Demultiplexer, Agere. [Online]. Available at: http://www.agere.com
8. M. C. Chow, Understanding SONET/SDH: Standards and Applications, Andan Publisher, 1995.
9. A. Romanow and R. Oskouy, 'A performance enhancement for packetized ABR and VBR + data,' ATM Forum 94-0295, Mar. 1994. [Online]. Available at: http://www.mfaforum.org
10. S. Floyd and V. Jacobson, 'Random early detection gateways for congestion avoidance,' IEEE/ACM Transactions on Networking, vol. 2, no. 4, pp. 397-413 (Aug. 1993).
11. Quality of Service (QoS) Networking, Cisco System, June 1999, white paper.
12. G. Armitage and K. Adams, 'Package reassembly during cell loss,' IEEE Network, vol. 7, no. 5, pp. 26-34 (Sept. 1993).
13. D. Stiliadis and A. Varma, 'A general methodology for design efficient traffic scheduling and shaping algortihms,' in Proc. IEEE INFOCOM'97, Kobe, Japan, pp. 326-335 (Apr. 1997).
14. J. C. R. Bennett and H. Zhang, 'Hierarchical packet fair queuing algorithms,' IEEE/ACM Transactions on Networking, vol. 5, no. 5, pp. 675-689 (Oct. 1997).
15. H. J. Chao and X. Guo, Quality of Service Control in High-Speed Networks, JohnWiley & Sons, Inc., Sept. 2001.
16. 'Juniper networks t-series core platforms,' Juniper Inc. [Online]. Available at: http://www.juniper.net/products/tseries/
17. R. Sudan and W. Mukai, Introduction to the Cisco CRS-1 Carrier Routing System, Cisco Systems, Inc, Jan. 1994.
18. Plugable fiber optic link (12 × 2.5 Gbps), Paracer. [Online]. Available at: http://www.paracer.com
19. M21150 and M21155 144 × 144 3.2 Gbps Crosspoint Switch, Mindspeed. [Online]. Available at: http://www.mindspeed.com
20. VC3003 140 × 140 Multi-Rate Crosspoint Switch with Clock, Data Recovery at Each Serial Input, Velio. [Online]. Available at: http://www.velio.com
21. M. Gupta and S. Singh, 'Greening of the Internet,' in Proc. ACM SIGCOMM03, Karlsruhe, Germany, pp. 19-26 (Aug. 2003).
22. 'ISO 9596, information processing systems, open system interconnection, management information protocol specification, common management information protocol.' ISO, Nov. 1990.
23. 'ISO 7498, information processing systems, open system interconnection, basic reference model part 4, OSI management framework.' ISO, Oct. 1986.
24. 'ISO/IEC DIS 10165-1, ISO/IEC DIS 10165-2, ISO/IEC DIS 10165-4, information processing systems, open system interconnection, structure of management information.' ISO, July 1990.
25. J. Case, R. Mundy, D. Partain, and B. Stewart, Introduction to Version 3 of the Internet-standard Network Management Framework, RFC 2570 (Informational), Apr. 1999, obsoleted by RFC 3410. [Online]. Available at: http://www.ietf.org/rfc/rfc2570.txt
26. U. Black, Network Management Standards: SNMP, CMIP, TMN, MIBs, and Object Libraries, 2nd ed., McGraw-Hill, 1994.
27. W. Stallings, SNMP, SNMPv2, SNMPv3, and RMON 1 and 2, Addison-Wesley, Massachusetts 1999.
28. SNMPv1, SNMPv2, and SNMPv3, SNMP Research International. [Online]. Available at: http://www.snmp.com
29. MIB compiler, MIB browser, and SNMP APIs, AdventNet, Inc. [Online]. Available at: http://www.adventnet.com/products/javaagent/snmp-agent-mibcompiler.html
30. M. Sanchez, E. W. Biersack, and W. Dabbous, "Survey and taxonomy of IP address lookup algorithms," IEEE Network, vol. 15, no. 2, pp. 8-23 (Mar. 2001).
31. V. Fuller, T. Li, J. Yu, and K. Varadhan, "Classless inter-domain routing (CIDR): an address assignment and aggregation strategy," RFC 1519 (Proposed Standard), Sept. 1993. [Online]. Available at: http://www.ietf.org/rfc/rfc1519.txt
32. Y. Rekhter andT. Li, "An architecture for IP address allocation with CIDR," RFC 1518 (Proposed Standard), Sept. 1993. [Online]. Available at: http://www.ietf.org/rfc/rfc1518.txt
33. P. Gupta, "Routing lookups and packet classifications: theory and practice," in Proc. HOT Interconnects 8, Stanford, California (Aug 2000).
34. D. Knuth, Fundamental Algorithms Vol. 3: Sorting and Searching. Addison-Wesley, Massachusetts, 1973.
35. W. Eatherton, "Hardware-based internet protocol prefix lookups," M. S. Thesis, Washington University, St. Louis, Missouri (May 1999).
36. V. Srinivasan and G. Varghese, "Faster IP lookups using controlled prefix expansion," in Proc. ACM SIGMATICS, Madison,Wisconsin, pp. 1-10 (June 1998).
37. D. R. Morrison, "PATRICIA-Practical algorithm to retrieve information coded in alfanumeric," IEEE/ACM Transactions on Networking, vol. 17, no. 1, pp. 1093-1102 (Oct. 1968).
38. S. Nilsson and G. Karlsson, "IP-Address lookup using LC-tries," IEEE Journal on Selected Areas in Communications, vol. 17, pp. 1083-1092 (June 1999).
39. M. Degermark, A. Brodnik, S. Carlsson, and S. Pink, "Small forwarding tables for fast routing lookups," in Proc. ACM SIGCOMM, Cannes, France, pp. 3-14 (Sept. 1997).
40. W. Eatherton, G. Varghese, and Z. Dittia, "Tree Bitmap: hardware/software IP lookups with incremental updates," ACM SIGCOMM Computer Communications Review, vol. 34, no. 2, pp. 97-122 (Apr. 2004).
41. F. Baboescu, D. M. Tullsen, G. Rosu, and S. Singh, "A tree based router search engine architecture with single port memories," ACM SIGARCH Computer Architecture News, vol. 33, pp. 123-133 (May 2005).
42. M.Waldvogel, G.Varghese, J. Turner, and B. Plattner, "Scalable high-speed IP routing lookups," in Proc. ACM SIGCOMM, Cannes, France, pp. 25-36 (Sept. 1997).
43. B. Lampson, V. Srinivasan, and G. Varghese, "IP lookups using multiway and multicolumn search," in Proc. IEEE INFOCOM'98 San Francisco, California, vol. 3, pp. 1248-1256 (Apr. 1998).
44. P. Gupta, S. Lin, and N. McKeown, "Routing lookups in hardware at memory access speeds," in Proc. IEEE INFOCOM'98, San Francisco, California, vol. 3, pp. 1240-1247 (Apr. 1998).
45. N. Huang, S. Zhao, J. Pan, and C. Su, "A fast IP routing lookup scheme for gigabit switching routers," in Proc. IEEE INFOCOM'99, NewYork, pp. 1429-1436 (Mar. 1999).
46. IDT75P52100 Network Search Engine, IDT, June 2003. [Online]. Available at: http://www.idt.com
47. CYNSE10512 Network Search Engine, CYPRESS, Nov. 2002. [Online]. Available at: http://www.cypress.com
48. Ultra9M-Datasheet from SiberCore Technologies. [Online]. Available at: http://www. sibercore.com [20] P. Gupta, "Algorithmic search solutions: features and benefits," in Proc. NPC-West 2003, San Jose, California (Oct 2003).
49. P.Gupta, "Algorithmic search solutions: features and benefits." in Proc. NPC-West 2003, San Jose, California, Oct. 2003
50. H. Liu, "Routing table compaction in ternary CAM," IEEE Micro, vol. 22, no. 1, pp. 58-64 (Jan. 2002).
51. F. Zane, G. Narlikar, and A. Basu, "Cool CAMs: power-efficient TCAMs for forwarding engines," in Proc. IEEE INFOCOM'03, San Francisco, California, pp. 42-52 (Apr. 2003).
52. K. Zheng, C. C. Hu, H. B. Lu, and B. Liu, "An ultra high throughput and power efficient TCAMbased IP lookup engine," in Proc. IEEE INFOCOM'04, Hong Kong, vol. 3, pp. 1984-1994 (Mar. 2004).
53. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed., Morgan-Kaufmann, San Francisco, California, 1995.
54. X. Zhang, B. Liu, W. Li, Y. Xi, D. Bermingham, and X. Wang, "IPv6-oriented 4 OC-768 packet classification with deriving-merging partition and field-variable encoding algorithm," in Proc. IEEE INFOCOM'06, Barcelona, Spain (Apr 2006).
55. "Route-view v6 database." [Online]. Available at: http://archive.routeviews.org/routeviews6/bgpdata/
56. Netlogic Microsystems. [Online]. Available at: http://www.netlogicmicro.com
57. D. Pao, "TCAM organization for IPv6 address lookup," in Proc. IEEE Int. Conf. on Advanced Communications Technology, Phoenix Park, South Korea, vol. 1, pp. 26-31 (Feb. 2005).
58. K. Zheng, Z. Liu, and B. Liu, "A scalable IPv6 route lookup scheme via dynamic variablestride bitmap compression and path compression," Computer Communication, vol. 29, no. 16, pp. 3037-3050 (Oct. 2006).
59. S. Lyer, R. R. Kompella, and A. Shelat, "ClassiPI: an architecture for fast and flexible packet classification," IEEE Network, vol. 15, no. 2, pp. 33-41 (Mar. 2001).
60. P. Gupta, "Routing lookups and packet classifications: theory and practice," in Proc. HOT Interconnects, Stanford, California (Aug 2000).
61. P. Gupta and N. Mckeown, "Algorithms for packet classification," IEEE Network, vol. 15, no. 2, pp. 24-32 (Mar. 2001).
62. V. Srinivasan, G.Varghese, S. Suri, and M.Waldvagel, "Fast and scalable layer four switching," in Proc. ACM SIGCOMM, Vancouver, Canada, pp. 191-202 (Aug. 1998).
63. F. Baboescu, S. Singh, and G.Varghese, "Packet classification for core routers: Is there an alternative to CAMs?" in Proc. IEEE INFOCOM'03, San Francisco, California, vol. 1, pp. 53-63 (2003).
64. G. Zhang and H. J. Chao, "Fast packet classification using field-level trie," in Proc. IEEE GLOBECOM'03, San Francisco, California, vol. 6, pp. 3201-3205 (Dec. 2003).
65. P. Gupta and N. Mckeown, "Packet classification on multiple fields," in Proc. ACM SIGCOMM'99, Harvard University, vol. 29, no. 4, pp. 147-160 (Aug. 1999).
66. T. V. Lakshman and D. Stiliadis, "High-speed policy-based packet forwarding using efficient multi-dimensional range matching," in Proc. ACMSIGCOMM,Vancouver, Canada, pp. 203-214 (Sep. 1998).
67. J. van Lunteren and T. Engbersen, "Fast and scalable packet classification," IEEE Journal on Selected Areas in Communications, vol. 21, pp. 560-571 (May 2003).
68. M. M. Buddhikot, S. Suri, and M.Waldvogel, "Space decomposition techniques for fast layer-4 switching," in Conf. Protocols for High Speed Networks, Holmdel, New Jersey, vol. 66, no. 6, pp. 277-283 (Aug. 1999).
69. P. Gupta and N. McKeown, "Classification using hierarchical intelligent cuttings," in Proc. HOT Interconnects VII, Stanford, California (Aug 1999).
70. S. Singh, F. Baboescu, G.Varghese, and J.Wang, "Packet classification using multidimensional cutting," in Proc. ACM SIGCOMM, Karlsruhe, Germany, pp. 213-224 (Aug. 2003).
71. V. Srinivasan, S. Suri, and G.Varghese, "Packet classification using tuple space search," in Proc. ACM SIGCOMM, Cambridge, Massachusetts, pp. 135-146 (Aug. 1999).
72. F. Baboesu and G. Varghese, "Scalable packet classification," in Proc. ACM SIGCOMM, San Diego, California, pp. 199-210 (Aug. 2001).
73. M. E. Kounavis, A. Kumar, H. Vin, R. Yavatkar, and A. T. Campbell, "Directions in packet classification for network processors," in Proc. SecondWorkshop on Network Processors (NP2), Anahein, California (Feb 2003).
74. E. Spitznagel, D. Taylor, and J. Turner, "Packet classification using extended TCAMs," in Proc. International Conference of Network Protocol (ICNP), Atlanta, Georgia, pp. 120-131 (Nov. 2003).
75. H. Che, Z. Wang, K. Zheng, and B. Liu, "Dynamic range encoding scheme for TCAM coprocessors," Technical report. [Online]. Available at: http://crystal.uta.edu/hche/dres.pdf.
76. H. Liu, "Efficient Mapping of range classifier into Ternary-CAM," in Proc. 10th Hot Interconnects, Stanford, California, pp. 95-100 (Aug. 2002).
77. S. Shenker and J. Wroclawski, Network element service specification template, RFC 2216 (Informational), Sept. 1997. [Online]. Available at: http://www.ietf.org/rfc/rfc2216.txt
78. "Data link provider interface (DLPI)," The Open Group, Jan. 2000.
79. H. J. Lee, M. S. Kim, W. K. Hong, and G. H. Lee, "QoS parameters to network performance metrics mapping for SLA monitoring," KNOM Review, vol. 5, no. 2 (Dec. 2002).
80. Z. Wang, Internet QoS: Architectures and Mechanisms for Quality of Service, Morgan Kaufmann, San Francisco, California, 2001.
81. S. Blake, D. Black, M. Carlson, E. Davies, Z. Wang, and W. Weiss, An architecture for differentiated service, RFC 2475 (Informational), Dec. 1998, updated by RFC 3260. [Online]. Available at: http://www.ietf.org/rfc/rfc2475.txt
82. Cisco. [Online]. Available at: http://www.cisco.com/univercd/cc/td/doc/product/software/ios120/12cgcr/qos_c/qcpart4/qcpolts.htm
83. S. Shenker and J. Wroclawski, General characterization parameters for integrated service network elements, RFC 2215 (Proposed Standard), Sept. 1997. [Online]. Available at: http://www.ietf.org/rfc/rfc2215.txt
84. D. Bertsekas and R. Gallager, Data Networks, 2nd ed., Prentice-Hall, Englewood Cliff, NJ, 1992.
85. N. McKeown, Packet switch architectures class. [Online].Available at: http://klamath.stanford. edu/~nickm
86. P. Marbach, "Priority service and max-min fairness," IEEE/ACM Transactions on Networking, vol. 11, no. 5, pp. 733-746 (Oct. 2003).
87. M. Shreedhar and G. Varghese, "Efficient fair queueing using deficit round-robin," IEEE/ACM Transactions on Networking, vol. 4, issue. 3, pp. 375-385 (June. 1996).
88. A. Parekh and R. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: the single node case," IEEE/ACMTransactions on Networking, vol. 1, issue. 2, pp. 344-357 (June. 1993).
89. A. Parekh and R. Gallager, "A generalized processor sharing approach to flow control in integrated services networks: the multiple node case," IEEE/ACM Transactions on Networking, vol. 2, issue. 2, pp. 137-150 (Apr. 1994).
90. D. Stiliadis, "Traffic scheduling in packet-switched networks: analysis, design, and implementation," Ph.D. Dissertation, University of California, Santa Cruz, June 1996.
91. J. Bennett, D. C. Stephens, and H. Zhang, "High speed, scalable, and accurate implementation of fair queueing algorithms inATM networks," in Proc. IEEE ICNP'97, Atlanta, Georgia, pp. 7-14 (1997).
92. L. Zhang, "Virtual clock: a new traffic control algorithm for packet switching networks," in Proc. ACM SIGCOMM, Philadelphia, Pennysylvania, pp. 19-29 (Sept. 1990).
93. S. J. Golestani, "Aself-clocked fair queueing scheme for broadband applications," in Proc. IEEE INFOCOM, Toronto, Canada, pp. 636-646 (June 1994).
94. D. Stiliadis and A.Varma, "Latency-rate servers: a general model for analysis of traffic scheduling algorithms," in Proc. IEEE INFOCOM, San Francisco, California, vol. 1, pp. 111-119 (Mar. 1996).
95. J. C. Bennett and H. Zhang, "WF2Q: worst-case fair weighted fair queueing," in Proc. IEEE INFOCOM, San Francisco, California, vol. 1, pp. 120-128 (Mar. 1996).
96. D. Stiliadis and A. Varma, "A general methodology for design efficient traffic scheduling and shaping algortihms," in Proc. IEEE INFOCOM'97, Kobe, Japan, vol. 1, pp. 326-335 (Apr. 1997).
97. D. Stiliadis and A. Varma, "Efficient fair queueing algorithms for packet-switched networks," IEEE/ACM Transactions on Networking, vol. 6, issue. 2, pp. 175-185 (Apr. 1998).
98. J. Bennett and H. Zhang, "Hierarchical packet fair queuing algorithms," IEEE/ACM Transactions on Networking, vol. 5, no. 5, pp. 675-689 (Oct. 1997).
99. S. Suri, G.Varghese, and G. Chandranmenon, "Leap forward virtual clock: a new fair queueing scheme with guaranteed delays and throughput fairness," in Proc. IEEE INFOCOM, Kobe, Japan, vol. 2, pp. 557-565 (Apr. 1997).
100. H. Chao, "A novel architecture for queue management in the ATM network," IEEE Journal on Selected Areas in Communications, vol. 9, issue. 7, pp. 1110-1118 (Sept. 1991).
101. H. Chao and N. Uzun, "A VLSI sequencer chip for ATM traffic shaper and queue manager," IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1634-1643 (Nov. 1992).
102. J. Nagle, Congestion control in IP/TCP internetworks, RFC 896, Jan. 1984. [Online].Available at: http://www.ietf.org/rfc/rfc896.txt
103. V. Jacobson, "Congestion avoidance and control," in Proc. ACM SIGCOMM '88, Stanford, California, vol. 18, no. 4, pp. 314-329 (Aug. 1988).
104. R. Braden, Requirements for Internet Hosts-Communication Layers, RFC 1122 (Standard), Oct. 1989. [Online.] Available at: http://www.ietf.org/rfc/rfc1122.txt
105. W. Stevens, TCP slow start, congestion avoidance, fast retransmit, and fast recovery algorithms, RFC 2001 (Proposed Standard), Jan. 1997, obsoleted by RFC 2581. [Online]. Available at: http://www.ietf.org/rfc/rfc2001.txt
106. W. Leland, M. Taqqu, W. Willinger, and D. Wilson, "On the self-similar nature of ethernet traffic (Extended Version)," IEEE/ACM Transactions on Networking, vol. 2, issue. 1, pp. 1-15 (Feb. 1994).
107. B. Braden, D. Clark, J. Crowcroft, B. Davie, S. Deering, D. Estrin, S. Floyd, V. Jacobson, G. Minshall, C. Partridge, L. Peterson, K. Ramakrishnan, S. Shenker, J. Wroclawski, and L. Zhang, Recommendations on queue management and congestion avoidance in the Internet, RFC 2309 (Informational), Apr. 1998. [Online]. Available at: http://www.ietf.org/rfc/rfc2309.txt
108. T.V. Lakshman, A. Neidhardt, and T. Ott, "The drop from front strategy in TCP overATMand its interworking with other control features," in Proc. IEEE INFOCOM, San Francisco, California, pp. 1242-1250 (Mar. 1996).
109. S. Floyd and V. Jacobson, "Random early detection gateways for congestion avoidance," IEEE/ACM Transactions on Networking, vol. 2, no. 4, pp. 397-413 (Aug. 1993).
110. Quality of Service (QoS) Networking, Cisco Systems, June 1999, white paper.
111. C. Villamizar and C. Song, "High performance TCP in ANSNET," Computer Communications Review, vol. 24, issue. 5, pp. 45-60 (Oct. 1994).
112. M. Gaynor, Proactive packet dropping methods for TCP gateways, Oct. 1996. [Online]. Available at: http://www.eecs.harvard.edu/~gaynor/final.ps
113. D. Clark and J. Wroclawski, "An approach to service allocation in the internet," July 1997, Internet Draft: draft-diff-svc-alloc-00.txt
114. K. Nichols, V. Jacobson, and L. Zhang, "A two-bit differentiated services architecture for the internet," Nov. 1997, Internet Draft: draft-nichols-diff-svc-arch-00.txt
115. D. Lin and R. Morris, "Dynamics of random early detection," in Proc. SIGCOMM, Cannes, France, pp. 127-137 (Sept. 1997).
116. T. Ott, T. Lakshman, and L. Wong, "SRED: stabilized RED," in Proc. IEEE INFOCOM, NewYork, NY, vol. 3, pp. 1346-1355 (Mar. 1999).
117. B. Suter, T. V. Lakshman, D. Stiliadis, and A. K. Choudhury, "Design considerations for supporting TCP with per-flow queueing," in Proc. IEEE INFOCOM, San Francisco, California, vol. 1, pp. 299-306 (Mar. 1998).
118. Y. S. Lin and C. B. Shung, "Quasi-pushout cell discarding," IEEE Communications Letters, vol. 1, issue. 5, pp. 146-148 (Sept. 1997).
119. F. A. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and E. Neri, "Packet scheduling in inputqueued cell-based switches," in Proc. IEEE INFOCOM'01, Anchorage, Alaska, vol. 2, pp. 1085-1094 (Apr. 2001).
120. F. A. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, "Packet-mode scheduling in input-queued cell-based switches," IEEE/ACM Transactions on Networking, vol. 10, no. 5, pp. 666-678 (Oct. 2002).
121. Y. Ganjali, A. Keshavarzian, and D. Shah, "Input queued switches: cell switching vs. packet switching," in Proc. IEEE INFOCOM'03, San Francisco, California, vol. 3, pp. 1651-1658 (Mar. 2003).
122. F. A. Tobagi, T. K. Kwok, and F. M. Chiussi, "Architecture, performance and implementation of the tandem banyan fast packet switch," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1173-1193 (Oct. 1991).
123. S. C. Liew and T. T. Lee, "N log N dual shuffle-exchange network with error-correcting routing," in Proc. IEEE ICC'92, vol. 1, Chicago, Illinois, pp. 1173-1193 (June 1992).
124. J. N. Giacopelli, J. J. Hickey,W. S. Marcus,W. D. Sincoskie, and M. Littlewood, "Sunshine: a high-performance self-routing broadband packet switch architecture," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1289-1298 (Oct. 1991).
125. A. Huang and S. Knauer, "STARLITE: a wideband digital switch," in Proc. IEEE GLOBECOM' 84, Atlanta, Georgia, pp. 121-125 (Dec. 1984).
126. M. J. Karol, M. Hluchyj, and S. Morgan, "Input vs. output queuing on a space-division packet switch," IEEE Transactions on Communications, vol. 35, no. 12, pp. 1347-1356 (Dec. 1987).
127. M. J. Karol, M. Hluchyj, and S. Morgan, "Input vs. output queuing on a space-division packet switch," IEEE Transactions on Communications, vol. 35, issue 12 (Dec. 1987).
128. N. McKeown, "Scheduling algorithms for input-queued cell switches," Ph.D. Thesis, UC Berkeley, May 1995.
129. N. McKeown, "iSLIP: a scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201 (Apr. 1999).
130. H. J. Chao, "Saturn: a terabit packet switch using Dual Round-Robin," IEEE Communications Magazine, vol. 38, issue. 12, pp. 78-84 (Dec. 2000).
131. D. N. Serpanos and P. I. Antoniadis, "FIRM: a class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 548-554 (Mar. 2000).
132. A. L. Gupta and N. D. Georganas, "Analysis of a packet switch with input and output buffers and speed constraints," in Proc. IEEE INFOCOM'91, Bal Harbour, Florida, vol. 2, pp. 694-700 (Apr. 1991).
133. J. S.-C. Chen and T. E. Stern, "Throughput analysis, optimal buffer allocation, and traffic imbalance study of a generic nonblocking packet switch," IEEE Journal on Selected Areas in Communications, vol. 9, no. 3, pp. 439-449 (Apr. 1991).
134. S. T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, "Matching output queueing with a combined input/output-queued switch," IEEE Journal on Selected Areas in Communications, vol. 17, no. 6, pp. 1030-1039 (June 1999).
135. B. Prabhakar and N. McKeown, "On the speedup required for combined input and output queued switching," Automatica, vol. 35, no. 12 (Dec. 1999).
136. S. Iyer and N. McKeown, "Using constraint sets to achieve delay bounds in CIOQ switches," IEEE Communications Letters, vol. 7, no. 6, pp. 275-277 (June 2003).
137. S. Iyer, A. Awadallah, and N. McKeown, "Analysis of a packet switch with memories running slower than the line-rate," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, vol. 2, pp. 529-537 (Mar. 2000).
138. S. Iyer and N. McKeown, "Making parallel packet switches practical," in Proc. IEEE INFOCOM'01, Anchorage, Alaska, vol. 3, pp. 1680-1687 (Apr. 2001).
139. S. Iyer and N. McKeown, "Analysis of the parallel packet switch architecture," IEEE/ACM Transactions on Networking, vol. 11, no. 2, pp. 314-324 (Apr. 2003).
140. H. J. Chao, Z. Jing, and S.Y. Liew, "Matching algorithms for three-stage bufferless Clos network switches," IEEE Communications Magazine, vol. 41, no. 10, pp. 46-54 (Oct. 2003).
141. A. Jajszczyk, "Nonblocking, repackable, and rearrangeable Clos networks: fifty years of the theory evolution," IEEE Communications Magazine, vol. 41, no. 10, pp. 28-33 (Oct. 2003).
142. H. Lee, K. H. Kook, C. S. Rim, K. P. Jun, and S. K. Lim, "A limited shared output buffer switch forATM," in Proc. Fourth Int. Conf. on Data Commun. Syst. and their Performance, Barcelona, Spain, pp. 163-179 (June 1990).
143. K. J. Schultz and P. G. Gulak, "CAM-based single-chip shared buffer ATM switch," in Proc. IEEE ICC'94, New Orleans, Louisiana, pp. 1190-1195 (May 1994).
144. K. Oshima, H. Yamanaka, H. Saito, H. Yamada, S. Kohama, H. Kondoh, and Y. Matsuda, "A new ATM switch architecture based on STS-type shared buffering and its LSI implementation," in Proc. IEICE'92,Yokohama, Japan, pp. 359-363 (Mar. 1992).
145. T. Cheney, J. A. Fingerhut, M. Flucke, and J. S. Turner, "Design of a Gigabit ATM switch," in Proc. IEEE INFOCOM'97, Kobe, Japan, vol. 1, pp. 2-11 (Apr. 1997).
146. K.Y. Eng and M. J. Karol, "State of the art in gigabit ATM switching," in Proc. IEEE BSS'95, Poznan, Poland, pp. 3-20 (Apr. 1995).
147. H. S. Kim, "Design and performance of multinet switch: a multistage ATM switch architecture with partially shared buffers," IEEE/ACM Transactions on Networking, vol. 2, no. 6, pp. 571-580 (Dec. 1994).
148. W. Fischer, O. Fundneider, E. H. Goeldner, and K. A. Lutz, "A scalable ATM switching system architecture," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1299-1307 (Oct. 1991).
149. T. R. Banniza, G. J. Eilenberger, B. Pauwels, andY. Therasse, "Design and technology aspects of VLSI's forATM switches," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1255-1264 (Oct. 1991).
150. J. Garcia-Haro andA. Jajszczyk, "ATMshared-memory switching architectures," IEEE Network, vol. 8, no. 4, pp. 18-26 (July 1994).
151. R. P. Bianchini, Jr. and H. S. Kim, "Design of a nonblocking shared-memory copy network for ATM," in Proc. IEEE INFOCOM'92, Florence, Italy, pp. 876-885 (May 1992).
152. H. Saito, H. Yamanaka, H. Yamada, M. Tuzuki, H. Kondoh, Y. Matsuda, and K. Oshima, "Multicast function and its LSI implementation in a shared multibuffer ATM switch," in Proc. IEEE INFOCOM'94, Toronto, Canada, vol. 1, pp. 315-322 (June 1994).
153. T. H. Lee and S. J. Liu, "Multicasting in a shared buffer memory switch," in Proc. IEEE TENCON'93, Beijing, People's Republic of China, pp. 209-212 (Oct. 1993).
154. N. McKeown, A. Mekkittikul, V. Anantharam, and J.Walrand, "Achieving 100% throughput in an input-queued switch," IEEE Transactions on Communications, vol. 47, no. 8, pp. 1260-1267 (Aug. 1999).
155. L. Tassiulas and A. Ephremides, "Stability properties of constrained queueing systems and scheduling policies for maximum throughput in multihop radio networks," IEEE Transactions on Automatic control, vol. 37, no. 12, pp. 1936-1949 (Dec. 1992).
156. R. E. Tarjan, "Data structures and network algorithms," in Proc. Society for Industrial and Applied Mathematics, Pennsylvania (Nov. 1983).
157. A. Mekkittikul and N. Mckeown, "A practical scheduling algorithm to achieve 100% throughput in input-queued switches," INFOCOM'98, San Francisco, California, pp. 792-799 (Mar. 1998).
158. D. Shah and M. Kopikare, "Delay bounds for approximate maximum weight matching algorithms for input queued switches," in Proc. IEEE INFOCOM'02, New York, pp. 1024-1031 (June 2002).
159. J. E. Hopcroft and R. M. Karp, "An n 5 2 algorithm for maximum matchings in bipartite graphs," SIAM, J. Comput., vol. 2, no. 4, pp. 225-231 (Dec. 1973).
160. N. McKeown, "Scheduling algorithms for input-queued cell switches," Ph.D. Thesis, UC Berkeley, May 1995.
161. J. G. Dai and B. Prabhakar, "The throughput of data switches with and without speedup," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 556-564 (Mar. 2000).
162. E. Leonardi, M. Mellia, F. Neri, and M. A. Marsan, "On the stability of input-queued switches with speed-up," IEEE/ACMTransactions on Networking, vol. 9, no. 1, pp. 104-118 (Feb. 2001).
163. T. E. Anderson, S. S. Owicki, J. B. Saxe, and C. P. Thacker, "High speed switch scheduling for local area networks," ACM Transactions on Computer Systems, vol. 11, no. 4, pp. 319-352 (Nov. 1993).
164. N. McKeown, "The iSLIP scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201 (Apr. 1999).
165. N. McKeown, P. Varaiya, and J. Warland, "Scheduling cells in an input-queued switch," IEE Electronics Letters, vol. 29, issue. 25, pp. 2174-2175 (Dec. 1993).
166. Y. Li, S. Panwar, and H. J. Chao, "On the performance of a dual round-robin switch," in Proc. IEEE INFOCOM 2001, Anchorage, Alaska, vol. 3, pp. 1688-1697 (Apr. 2001).
167. Y. Li, "Design and analysis of schedulers for high speed input queued switches," Ph.D. Dissertation, Polytechnic University, Brooklyn, NewYork, Jan. 2004.
168. D. N. Serpanos and P. I. Antoniadis, "FIRM: a class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 548-554 (Mar. 2000).
169. H. J. Chao and J. S. Park, "Centralized contention resolution schemes for a large-capacity optical ATM switch," in Proc. IEEE ATM Workshop, Fairfax, Virginia (May 1998).
170. H. J. Chao, "Satur: A terabit packet switch using dual round-robin," IEEE Communications Magazine, vol. 38, no. 12, pp. 78-84 (Dec. 2000).
171. E. Oki, R. Rojas-Cessa, and H. J. Chao, "A pipeline-based maximal-sized matching scheme for high-speed input-buffered switches," IEICE Transactions on Communications, vol. E85-B, no. 7, pp. 1302-1311 (July 2002).
172. A. Smiljanic, R. Fan, and G. Ramamurthy, "RRGS-round-robin greedy scheduling for electronic/optical terabit switches," in Proc. IEEE GLOBECOM'99, Rio de Janeireo, Brazil, pp. 1244-1250 (Dec. 1999).
173. H.Takagi, "Queueing analysis of polling models: an update," in Stochastic Analysis of Computer and Communication Systems. Elsevier Science Inc., NewYork; pp. 267-318, 1990.
174. Y. Li, S. Panwar, and H. J. Chao, "The dual round-robin matching switch with exhaustive service," in Proc. High Performace Switching and Routin (HPSR) 2002, Kobe, Japan (May 2002).
175. P. Giaccone, B. Prabhakar, and D. Shah, "Towards simple, high-performance schedulers for high-aggregate bandwidth switches," in Proc. IEEE INFOCOM'02, New York, vol. 3, pp. 1160-1169 (2002).
176. L. Tassiulas, "Linear complexity algorithms for maximum throughput in radio networks and input queued switches," in Proc. IEEE INFOCOM'98, San Francisco, California, vol. 2, pp. 533-539 (Mar. 1998).
177. A. Nijenhuis and H. Wilf, Combinatorial Algorithms: for Computers and Calculators. Academic Press, Orlando, Florida, 1978.
178. P. Giaccone, B. Prabhakar, and D. Shah, "Randomized scheduling algorithms for high-aggregate bandwidth switches," IEEE Journal on Selected Areas in Communications, vol. 21, no. 4, pp. 546-559 (May 2003).
179. D. Shah, P. Giaccone, and B. Prabhakar, "Efficient randomized algorithms for input-queued switch scheduling," IEEE Micro, vol. 22, no. 1, pp. 10-18 (Jan. 2002).
180. Y. Li, S. Panwar, and H. J. Chao, "Exhaustive service matching algorithms for input queued switches," in Proc. Workshop on High Performance Switching and Routing (HPSR 2004), Phoenix, Arizona (Apr 2004).
181. L. Kleinrock and H. Levy, "The analysis of random polling systems," Operations Research, vol. 36, no. 5, pp. 716-732 (Sept. 1988).
182. Y. Li, S. Panwar, and H. J. Chao, "Performance analysis of a dual round robin matching switch with exhaustive service," in Proc. IEEE GLOBECOM'02, Taipei, Taiwan, vol. 3, pp. 2292-2297 (Nov. 2002).
183. F. A. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and E. Neri, "Packet scheduling in inputqueued cell-based switches," in Proc. IEEE INFOCOM'01, Anchorage, Alaska, vol. 2, pp. 1085-1094 (Apr. 2001).
184. K. Claffy, G. Miller, and K. Thompson, "The nature of the beast: recent traffic measurements from an Internet backbone," in Proc. INET'98, Geneva, Switzerland, pp. 21-24 (July 1998).
185. B. Towles andW. Dally, "Guaranteed scheduling for switches with configuration overhead," in Proc. IEEE INFOCOM'02, NewYork, vol. 1, pp. 342-351 (June 2002).
186. T. Inukai, "An efficient SS/TDMA time slot assignment algorithm," IEEE Transactions on Communications, vol. 27, no. 10, pp. 1449-1455 (Oct. 1979).
187. C. S. Chang, W. J. Chen, and H. Y. Huang, "Birkhoff-von Neumann input buffered crossbar switches," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 1614-1623 (Mar. 2000).
188. B. Towles andW. J. Dally, "Guaranteed scheduling for switches with configuration overhead," IEEE/ACM Transactions on Networking, vol. 11, no. 5, pp. 835-847 (Oct. 2003).
189. R. Cole and J. Hopcroft, "On edge coloring bipartite graph," SIAM Journal on Computing, vol. 11, no. 3, pp. 540-546 (1982).
190. Y. Li, S. Panwar, and H. J. Chao, "Frame-based matching algorithms for optical switches," in Proc. IEEEWorkshop on High Performance Switching and Routing (HPSR 2003), Torino, Italy, pp. 97-102 (June 2003).
191. D. Gale and L. S. Shapley, "College admission and the stability of marriage," American Mathematical Monthly, vol. 69, no. 1, pp. 9-15 (1962).
192. D. Gusfield and R. Irving, The Stable Marriage Problem: Structure and Algorithms. The MIT Press, Cambridge, Massachusetts, 1989.
193. B. Prabhakar and N. McKeown, "On the speedup required for combined input and output queued switching," Automatica, vol. 35, issue. 12, pp. 1909-1920 (Dec. 1999).
194. S. T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, "Matching output queuing with a combined input/output-queued switch," IEEE Journal on Selected Areas in Communications, vol. 17, no. 6, pp. 1030-1039 (June 1999).
195. P. Krishna, N. Patel, A. Charny, and R. Simcoe, "On the speedup required for work-conversing crossbar switches," IEEE Journal on Selected Areas in Communications, vol. 17, no. 6, pp. 1057-1066 (June 1999).
196. C. Clos, "A study of non-blocking switching network," Bell System Technical Journal, vol. 32, no. 2, pp. 404-426 (Mar. 1953).
197. V. E. Benes, "Optimal rearrangeable multistage connecting networks," Bell System Technical Journal, vol. 43, pp. 1641-1656 (July 1964).
198. J. S. Turner and L. F. Wyatt, "A packet network architecture for integrated services," in Proc. Globecom'83, San Diego, California, pp. 2.1.1-2.1.6 (Nov 1983).
199. J. J. Kulzer and W. A. Montgomery, "Statistical switching architecture for future services," in Proc. ISS'84, Florence, Italy, pp. 22A.4.1-22A.4.6 (May 1984).
200. J. S. Turner, "Design of a broadcast packet switching network," IEEE Transaction on Communications, vol. 36, pp. 734-743 (June 1998).
201. L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning multiprocessor systems," in Proc. 1st Annu. Int. Symp. Comput. Architecture, Gainesville, Florida, pp. 21-28 (Dec. 1973).
202. K. E. Batcher, "Sorting networks and their application," in Proc. Spring Joint Comput. Conf. AFIPS,Washington, DC, pp. 307-314 (1968).
203. B. Bingham and H. Bussey, "Reservation-based contention resolution mechanism for Batcherbanyan packet switches," Electronic Letters, vol. 24, no. 13, pp. 772-773 (June 1988).
204. J. N. Giacopelli, J. J. Hickey,W. S. Marcus,W. D. Sincoskie, and M. Littlewood, "Sunshine: a high-performance self-routing broadband packet switch architecture," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1289-1298 (Oct. 1991).
205. F. A. Tobagi and T.Kwok, "The tandem banyan switching fabric: a simple high-performance fast packet switch," in Proc. IEEE INFOCOM'91, Bal Harbour, Florida, pp. 1245-1253 (Apr. 1991).
206. S. C. Liew and T. T. Lee, "N logN dual shuffle-exchange network with error-correcting routing," IEEE Transactions on Communications, vol. 42, no. 2, pp. 754-766 (Feb. 1994).
207. T. T. Lee, "Nonblocking copy networks for multicast packet switching," IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, pp. 1455-1467 (Dec. 1988).
208. Y.-S.Yeh, M. G. Hluchyj, andA. S.Acampora, "The knockout switch:Asimple, modular architecture for high-performance packet switching," IEEE Journal on Selected Areas in Communications, vol. 5, no. 8, pp. 1274-1283 (Oct. 1987).
209. W. Hoeffding, "On the distribution of the number of successes in independent trials," Ann. Math. Statist., vol. 27, pp. 713-721 (1956).
210. A. Pattavina, "Multichannel bandwidth allocation in a broadband packet switch," IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, pp. 1489-1499 (Dec. 1988).
211. M. G. Hluchyj and M. J. Karol, "Queueing in high-performance packet switching," IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, pp. 1587-1597 (Dec. 1988).
212. S. C. Liew and K. W. Lu, "Performance analysis of asymmetric packet switch modules with channel grouping," in Proc. IEEE INFOCOM'90, San Francisco, California, pp. 668-676 (June 1990).
213. Y. Oie, M. Murata, K. Kubota, and H. Miyahara, "Effect of speedup in nonblocking packet switch," in Proc. ICC'89, Boston, Massachusetts, pp. 410-415 (June 1989).
214. K. Y. Eng, M. J. Karol, and Y.-S. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," IEEE Transactions on Communications, vol. 40, no. 2, pp. 423-430 (Feb. 1992).
215. H. J. Chao, "A recursive modular terabit/second ATM switch," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1161-1172 (Oct. 1991).
216. H. J. Chao, B. S. Choe, J. S. Park, and N. Uzun, "Design and implementation of Abacus switch: A scalable multicastATM switch," IEEE Journal on Selected Areas in Communications, vol. 15, no. 5, pp. 830-843 (June 1997).
217. J. Hui and E. Arthurs, "A broadband packet switch for integrated transport," IEEE Journal on Selected Areas in Communications, vol. 5, no. 8, pp. 1264-1273 (Oct. 1987).
218. B. Bingham and H. Bussey, "Reservation-based contention resolution mechanism for Batcherbanyan packet switches," Electronics Letters, vol. 24, no. 13, pp. 772-773 (June 1988).
219. A. Cisneros and C. A. Bracket, "A largeATM switch based on memory switches and optical star couplers," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1348-1360 (Oct. 1991).
220. R. Handel, M. N. Huber, and S. Schroder, ATM networks: Concepts, Protocols, Applications. Addison-Wesley Publishing Company, Reading, MA, 1994, Chapter 7.
221. M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input versus output queuing on a space-division packet switch," IEEE Transactions on Communications, vol. 35, pp. 1347-1356 (Dec. 1987).
222. Y. Oie, M. Murata, K. Kubota, and H. Miyahara, "Effect of speedup in nonblocking packet switch," in Proc. ICC'89, Boston, Massachusetts, pp. 410-415 (June 1989).
223. A. Pattavina, "Multichannel bandwidth allocation in a broadband packet switch," IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, pp. 1489-1499 (Dec. 1988).
224. S. C. Liew and K. W. Lu, "Comparison of buffering strategies for asymmetric packet switch modules," IEEE Journal on Selected Areas in Communications, vol. 9, no. 3, pp. 428-438 (Apr. 1991).
225. T. Kozaki, N. Endo, Y. Sakurai, O. Matsubara, M. Mizukami, and K. Asano, "32 × 32 shared buffer type ATM switch VLSI's for B-ISDN's," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1239-1247 (Oct. 1991).
226. C. Y. Chang, A. J. Paulraj, and T. Kailath, "A broadband packet switch architecture with input and output queuing," in Proc. IEEE GLOBECOM'94, San Francisco, California, pp. 448-452 (Nov. 1994).
227. A. Pattavina and G. Bruzzi, "Analysis of input and output queuing for nonblocking ATM switches," IEEE/ACM Transactions on Networking, vol. 1, no. 3, pp. 314-328 (June 1993).
228. H. J. Chao and N. Uzun, "AnATM routing and concentration chip for a scalable multicastATM switch," IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 816-828 (June 1997).
229. E. P. Rathgeb, W. Fischer, C. Hinterberger, E. Wallmeier, and R. Wille-Fier, "The Main-Streetxpress core services node-a versatile ATM switch architecture for the full service network," IEEE J. on Selected Areas in Communications, vol. 15, no. 5, pp. 830-843 (June 1997).
230. K.Y. Eng and M. J. Karol, "State-of-the-art in gigabit ATM switching," in Proc. IEEE BSS'95, Poznan, Poland, pp. 3-20 (Apr. 1995).
231. I. Widjaja and A. I. Elwalid, "Performance issues in VC-merge capable switches for IP over ATM networks," in Proc. INFOCOM'98, San Francisco, California, pp. 372-380 (Mar. 1998).
232. S.-T. Chuang, S. Iyer, and N. Mckeown, "Practical algorithm for performance guarantees in buffered crossbars," in Proc. IEEE INFOCOM'05, Miami, Florida, vol. 2, pp. 981-991 (Mar. 2005).
233. G. Passas and M. Katevenis, "Packet mode scheduling in buffered crossbar (CICQ) switches," in Proc. High Performance Switching and Routin (HPSR) 2006, Poznan, Poland (June 2006).
234. Y. Doi and N.Yamanaka, "A high-speedATM switch with input and cross-point buffers," IEICE Transactions on Communications, vol. E76-B, no. 3, pp. 310-314 (Mar. 1993).
235. M. Nabeshima, "Performance evaluation of a combined input-and crosspoint-queued switch," IEICE Transactions on Communications, vol. E83-B, no. 3, pp. 737-741 (Mar. 2000).
236. Rojas-Cessa, E. Oki, and H. J. Chao, "CIXOB-k: Combined input-crosspoint-output buffered packet switch," in Proc. IEEE GLOBECOM'01, San Antonio, Texas, pp. 2654-2660 (Nov. 2001).
237. N. McKeown, "iSLIP: a scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201 (Apr. 1999).
238. R. Rojas-Cessa, E. Oki, Z. Jing, and H. J. Chao, "CIXB-1: combined input-one-cell-crosspoint buffered switch," in Proc. IEEEWorkshop on High Performance Switching and Routing, Dallas, Texas, pp. 324-329 (May 2001).
239. R. Schoenen, G. Post, and G. Sander, "Weighted arbitration algorithms with priorities for input-queued switches with 100% throughput," in Proc. Broadband Switching Symposium'99, Kingston, Canada, 1999. [Online]. Available at: http://www.schoenenservice.de/assets/papers/Schoenen99bssw.pdf
240. C. S. Chang, D. S. Lee, and Y. S. Jou, "Load balanced Birkhoff-von Neumann switches," in Proc. IEEE HPSR 2001, Dallas, Texas, pp. 276-280 (May 2001).
241. B. Li, M. Hamdi, and X.-R. Cao, "An efficient scheduling algorithm for input-queuing ATM switches," in Proc. IEEE Broadband Switching Systems'97, Taiwan, pp. 148-154 (Dec. 1997).
242. E. Oki and N.Yamanaka, "A high-speedATM switch based on scalable distributed arbitration," IEICE Transactions Communications, vol. E80-B, no. 9, pp. 1372-1376 (Sept. 1997).
243. N. McKeown, "Scheduling algorithms for input-queued cell switches," Ph.D. Thesis, UC Berkeley, May 1995.
244. T. Javidi, R. Magill, and T. Hrabik, "A high throughput scheduling algorithm for a buffered crossbar switch fabric," in Proc. IEEE International Conference on Communications, Helsinki, Finland, vol. 5, pp. 1586-1591 (June 2001).
245. J. G. Dai and B. Prabhakar, "The throughput of data switches with and without speedup," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 556-564 (Mar. 2000).
246. L. Mhamdi and M. Hamdi, "MCBF: a high-performance scheduling algorithm for buffered crossbar switches," IEEE Communications Letters, vol. 7, no. 9, pp. 451-553 (Sept. 2003).
247. J. Hopcroft and R. Karp, "An n 5/2 algorithm for maximum matchings in bipartite graphs," SIAM Journal on Computing, vol. 2, no. 4, pp. 225-231 (1973).
248. R. Cole and J. Hopcroft, "On edge coloring bipartite graph," SIAM Journal on Computing, vol. 11, no. 3, pp. 540-546 (1982).
249. H. J. Chao, C. Lam, and E. Oki, Broadband Packet Switching Technologies-A Practical Guide to ATM Switches and IP Routers. JohnWiley & Sons, Inc., Hoboken, New Jercy, 2001.
250. H. J. Chao and S. Y. Liew, "A new optical cell switching paradigm," in Proc. International Workshop on Optical Burst Switching, Dallas, Texas, pp. 120-132 (Oct. 2003).
251. E. Oki, Z. Jing, R. Rojas-Cessa, and H. J. Chao, "Concurrent round-robin-based dispatching schemes for Clos-network switches," IEEE/ACM Transactions on Networking, vol. 10, no. 6, pp. 830-844 (Dec. 2002).
252. Y. Li, S. Panwar, and H. J. Chao, "The dual round-robin matching switch with exhaustive service," in Proc. High Performace Switching and Routin (HPSR) 2002, Kobe, Japan (May 2002).
253. N. McKeown, "iSLIP: a scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201 (Apr. 1999).
254. F. M. Chiussi, J. G. Kneuer, andV. P. Kumar, "Low cost scalable switching solutions for broadband networking: the ATLANTA architecuture and chipset," IEEE Communications Magazine, vol. 35, issue. 12, pp. 44-53 (Dec. 1997).
255. M. Karol and C.-L. I, "Performance analysis of a growable architecture for broadband packet (ATM) switching," in Proc. IEEE GLOBECOM'89, Dallas, Texas, pp. 1173-1180 (Nov. 1989).
256. F. T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays · Trees · Hypercubes. Morgan Kaufmann, San Francisco, California, 1992.
257. R. J.Wilson, Introduction to Graph Theory. Academic Press, NewYork, 1972.
258. R. J. McEliece, R. B. Ash, and C. Ash, Introduction to Discrete Mathematics. McGraw-Hill, NewYork, 1989.
259. T. T. Lee and S. Y. Liew, "Parallel algorithm for benes networks," in Proc. IEEE INFOCOM '96, San Francisco, California (Mar 1996).
260. H. J. Chao, "Next generation routers," IEEE Proceedings, vol. 90, no. 9, pp. 1518-1558 (Sept. 2002).
261. C. Clos, "A study of non-blocking switching networks," Bell System Technical Journal, vol. 32, no. 3, pp. 406-424 (Mar. 1953).
262. R. Sudan andW. Mukai, Introduction to the Cisco CRS-1 Carrier Routing System, Cisco Systems, Inc., San Jose, California (Jan. 1994).
263. H. J. Chao, J. S. Park, S. Artan, S. Jiang, and G. Zhang, "TrueWay:A highly scalable multi-plane multi-stage buffered packet switch," in Proc. IEEE Workshop on High Performance Switching and Routing, Hong Kong, pp. 246-253 (May 2005).
264. H. T. Kung, T. Blackwell, and A. Chapman, "Credit-based flow control for ATM networks: Credit update protocol, adaptive credit allocation, and statistical multiplexing," in Proc. ACM SIGCOMM, London, United Kingdom, pp. 101-115 (Aug. 1994).
265. Y. C. Jung, C. K. Un, S. M. Ryu, and S. C. Lee, "Analysis of out-of-sequence problem and preventative schemes in parallel switch architecture for high-speedATM network," Proceedings of the IEEE, vol. 141, no. 1, pp. 29-38 (Feb. 1994).
266. N. McKeown, "iSLIP: a scheduling algorithm for input-queued switches," IEEE/ACM Transactions on Networking, vol. 7, no. 2, pp. 188-201 (Apr. 1999).
267. H. J. Chao, "Saturn: a terabit packet switch using dual round-robin," IEEE Communications magazine, vol. 38, no. 12, pp. 78-84 (Dec. 2000).
268. C. S. Chang, D. Lee, and Y. Jou, "Load balanced Birkhoff-von Neumann switches. Part I: One-stage buffering," Computer Communications, vol. 25, no. 6, pp. 611-622 (2002).
269. G. Birkhoff, "Tres observaciones sobre el algebra lineal," Univ. Nac. Tucum an Rev. Ser. A, vol. 5, pp. 147-151 (1946).
270. J. von Neumann, "A certain zero-sum two-person game equivalent to the optimal assignment problem," in Contributions to the Theory of Games. Princeton University Press, Princeton, NJ, vol. 2, pp. 5-12, 1982.
271. C. Chang,W. Chen, and H. Huang, "On service guarantees for input buffered crossbar switches: a capacity decomposition approach by Birkhoff and von Neumann," in Proc. IEEE IWQOS'99, London, UK, pp. 79-86 (June 1999).
272. C. S. Chang, W. J. Chen, and H. Y. Huang, "Birkhoff-von Neumann input buffered crossbar switches," in Proc. IEEE INFOCOM'00, Tel Aviv, Israel, pp. 1614-1623 (Mar. 2000).
273. C. Chang, D. Lee, andY. Jou, "Load balanced Birkhoff-von Neumann switche. Part II: Multistage buffering," Computer Communications, vol. 25, no. 6, pp. 623-634 (2002).
274. I. Keslassy and N. McKeown, "Maintaining packet order in two-stage switches," in Proc. IEEE INFOCOM'02, NewYork, vol. 2, pp. 1032-1041 (June 2002).
275. I. Keslassy, S. Chuang, K.Yu, D. Miller, M. Horowitz, O. Solgaard, and N. McKeown, "Scaling Internet routers using optics," in Proc. ACM SIGCOMM, Karlsruhe, Germany, pp. 189-200 (Aug. 2003).
276. C. S. Chang, D. Lee, andY. J. Shih, "Mailbox switch: A scalable two-stage switch architecture for conflict resolution of ordered packets," in Proc. IEEE INFOCOM'04, Hong Kong, vol. 3, pp. 1995-2006 (Mar. 2004).
277. Y. Shen, S. Jiang, S. Panwar, and H. J. Chao, "Byte-Focal: a practical load balanced switch," in Proc. IEEE Workshop on High Performance Switching and Routing (HPSR'05), Hong Kong, pp. 6-12 (May 2005).
278. Y. Li, S. Panwar, and H. J. Chao, "Exhaustive service matching algorithms for input queued switches," in Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 04), Phoenix, Arizona, pp. 253-258 (Apr. 2004).
279. P. Giaccone, B. Prabhakar, and D. Shah, "Towards simple, high-performance schedulers for high-aggregate bandwidth switches," in Proc. IEEE INFOCOM'02, NewYork, vol. 3, pp. 1160-1169 (June 2002).
280. W. Leland, M. Taqqu, W. Willinger, and D. Wilson, "On the self-similar nature of ethernet traffic (Extended Version)," IEEE/ACM Transactions on Networking, vol. 2, issue. 1, pp. 1-15 (Feb. 1994).
281. P. E. Green, Fiber Optic Communication Networks. Prentice-Hall, Upper Saddle River, New Jercy, 1992.
282. N. V. Srinivasan, "Add-drop multiplexers and cross-connects for multiwavelength optical networking," in Proc. Tech. Dig., OFC'98, San Jose, California, pp. 57-58 (Feb. 1998).
283. C. K. Chan, F. Tong, L. K. Chen, and K. W. Cheung, "Demonstration of an add-drop network node with time slot access for high-speed WDMA dual bus/ring packet networks," in Proc. Tech. Dig., OFC'98, San Jose, California, pp. 62-64 (Feb. 1998).
284. G. Chang, G. Ellinas, J. K. Gamelin, M. Z. Iqbal, and C. A. Brackett, "Multiwavelength reconfigurableWDM/ATM/SONET network testbed," IEEE/OSA Journal of Lightwave Technology, vol. 14, issue. 6, pp. 1320-1340 (June. 1996).
285. R. E.Wanger, R. C. Alferness, A. A. M. Saleh, and M. S. Goodman, "MONET: Multiwavelength optical networking," IEEE/OSA Journal of Lightwave Technology, vol. 14, issue. 6, pp. 1349-1355 (June. 1996).
286. S. Okamoto and K. Sato, "Optical path cross-connect systems for photonic transport networks," in Proc. IEEE Global Telecommun. Conf., Houston, Texas, pp. 474-480 (Nov. 1993).
287. A. K. Srivastava, J. L. Zyskind, Y. Sun, J. W. Sulhoff, C. Wolf, M. Zirngibl, R. Monnard, A. R. Charplyvy, A. A. Abramov, R. P. Espindola, T. A. Strasse, J. R. Pedrazzani, A. M.Vengsarkar, J. Zhou, and D. A. Ferrand, "1 Tb/s transmission of 100WDM10 Gb/s channels over 400 km of TrueWaveTM fiber," in Postdeadline Papers, OFC'98, San Jose, California, pp. PD10-1-PD10-4 (Feb. 1998).
288. A. S. Tanenbaum, Computer Networks. Prentice-Hall, New Jersey, 1981.
289. E. Arthurs, M. S. Goodman, H.Kobrinski, and M. P.Vecchi, "HYPASS: an optoelectronic hybrid packet switching system," IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, pp. 1500-1510 (Dec. 1988).
290. T. T. Lee, M. S. Goodman, and E. Arthurs, "STAR-TRACK: a broadband optical multicast switch," Bellcore Technical Memorandum Abstract, 1989.
291. A. Cisneros and C. A. Brackett, "A largeATM switch based on memory switches and optical star couplers," IEEE Journal on Selected Areas in Communications, vol. 9, no. 8, pp. 1348-1360 (Oct. 1991).
292. M. J. Karol, M. G. Hluchyj, and S. P. Morgan, "Input versus output queueing on a space division packet switch," IEEE Transactions on Communications, vol. COM-35, no. 12, pp. 1347-1356 (Dec. 1987).
293. E. Munter, L. Parker, and P. Kirkby, "A high-capacityATM switch based on advanced electronic and optical technologies," IEEE Communications Magazine, vol. 33, issue. 11, pp. 64-71 (Nov. 1995).
294. Y. Nakahira, H. Inoue, and Y. Shiraishi, "Evaluation of photonic ATM switch architectureproposal of a new switch architecture," in Proc. International Switching Symposium, Berlin, Germany, pp. 128-132 (1995).
295. H. J. Chao and T.-S.Wang, "Design of an optical interconnection network for terabit IP router," in Proc. IEEE LEOS'98, Orlando, Florida, vol. 1, pp. 233-234 (Dec. 1998).
296. D. Lesterlin, S. Artigaud, and H. Haisch, "Integrated laser/modulators for 10 Gbit/s system," in Proc. 22nd European Conference on Optical Communication (ECOC'96), Olso, Norway, pp. 3.183-3.190 (Sep. 1996).
297. M. G. Young, U. Koren, B. I. Milter, M. A. Newkirk, M. Chien, M. Zirngibl, C. Dragone, B.Tell, H. M. Presby, and G. Raybon, "A16 × 1wavelength division multiplexer with integrated distributed Bragg reflector laser and electroabsorption modulators," IEEE Photonics Technology Letters, vol. 5, no. 8, pp. 908-910 (Aug. 1993).
298. K. C. Syao, K. Yang, X. Zhang, G. I. Haddad, and P. Bhattacharya, "16-channel monolithically integrated InP-based p-i-n/HBT photoreceiver array with 11-GHz channel bandwidth and low crosstalk," in Proc. Optical Fiber Communication (OFC'97), Dallas, Texas, pp. 15-16 (Feb. 1997).
299. I. Ogawa, F. Ebisawa, F. Hanawa, T. Hashimoto, M. Yanagisawa, K. Shuto, T. Ohyama, Y. Yamada, Y. Akahori, A. Himeno, K. Kato, N. Yoshimoto, and Y. Tohmon, "Lossless hybrid integrated 8-ch optical wavelength selector module using PLC platform and PLC-PLC direct attachment techniques," in Proc. Optical Fiber Communication Conference (OFC'98), San Jose, California, pp. 1-4 (Feb. 1998).
300. O. Ishida, H. Takahashi, andY. Inoue, "Digitally tunable optical filters using arrayed-waveguide grating (AWG)multiplexers and optical switches," IEEE/OSAJournal of LightwaveTechnology, vol. 15, no. 2, pp. 321-327 (1997).
301. K. Yamakoshi, K. Nakai, N. Matsuura, E. Oki, R. Kawano, and N. Yamanaka, "5-Tbit/s frame-based ATM switching system using 2.5-Gbit/s/spl times/8 optical WDM," in Proc. IEEE International Conference on Communications, Helsinki, Finland, vol. 10, pp. 3117-3121 (June 2001).
302. C. K. Chan, K. L. Sherman, and M. Zirngibl, "Afast 100-channelwavelength-tunable transmitter for optical packet switching," IEEE Photonics Technology Letters, vol. 13, issue. 7, pp. 729-731 (July. 2001).
303. K. R. Tamura, Y. Inoue, K. Sato, T. Komukai, A. Sugita, and M. Nakazawa, "A discretely tunable mode-locked laser with 32 wavelengths and 100-GHz channel spacing using an arrayed waveguide grating," IEEE Photonics Technology Letters, vol. 13, issue. 11, pp. 1227-1229 (Nov. 2001).
304. S. Nakamura, Y. Ueno, and K. Tajima, "168-Gb/s all-optical wavelength conversion with a symmetric-Mach-Zehnder-type switch," IEEE Photonics Technology Letters, vol. 13, issue. 10, pp. 1091-1093 (Oct. 2001).
305. J. Leuthold, B. Mikkelsen, G. Raybon, C. H. Joyner, J. L. Pleumeekers, B. I. Miller, K. Dreyer, and R. Behringer, "All-optical wavelength conversion between 10 and 100 Gb/s with SOA delayed-interference configuration," Optical and Quantum Electronic, vol. 33, no. 7-10, pp. 939-952 (2001).
306. H. Takara, S. Kawanishi,Y.Yamabayashi,Y. K. Tohmori, K. Takiguchi,Y. K. Magari, I. Ogawa, and A. Himeno, "Integrated optical-time division multiplexer based on planar lightwave circuit," Electronics Letters, vol. 35, issue. 15, pp. 1263-1264 (1999).
307. D.T. K.Tong, K.-L. Deng, B. Mikkelsen, G. Ranbon, K. F. Dreyer, and J. E. Johnson, "160 Gbit/s clock recovery using electroabsorption modulator-based phase-locked loop," Electronics Letters, vol. 36, no. 23, pp. 1951-1952 (2000).
308. K.-L. Deng, D. T. K. Tong, C.-K. Chan, K. F. Dreyer, and J. E. Johnson, "Rapidly reconfigurable optical channel selector using RF digital phase shifter for ultra-fast OTDM networks," Electronics Letters, vol. 36, no. 20, pp. 1724-1725 (2000).
309. Z. Hass, "The "staggering switch": an electrically controlled optical packet switch," IEEE Journal of Lightwave Technology, vol. 11, no. 5, pp. 925-936 (May 1993).
310. D. Chiaroni, C. Chauzat, D. D. Bouard, and M. Sotom, "Sizeability analysis of a high-speed photonic packet switching architecture," in Proc. 21st Eur. Conf. on Opt. Comm. (ECOC'95), Brussels, Belgium, pp. 793-796 (Sep. 1995).
311. G. H. Duan, J. R. Fernandez, and J. Garabal, "Analysis of ATM wavelength routing systems by exploring their similitude with space division switching," in Proc. IEEE International Conference on Communication, Dallas, Texas, vol. 3, pp. 1783-1787 (June 1996).
312. Y. Chai, J. H. Chen, F. S. Choa, J. P. Zhang, J. Y. Fan, and W. Lin, "Scalable and modularized optical random access memories for optical packet switching networks," in Proc. CLEO'98, San Francisco, California, pp. 397 (May 1998).
313. Y. Chai, J. H. Chen, X. J. Zhao, J. P. Zhang, J.Y. Fan, F. S. Choa, andW. Lin, "Optical DRAMs using refreshable WDM loop memories," in Proc. ECOC'98, Madrid, Spain, pp. 171-172 (Sep. 1998).
314. R. Langenhorst, M. Eiselt,W. Pieper, G. Groossleupt, R. Ludwig, L. Kuller, "Fiber loop optical buffer," IEEE Journal of Lightwave Technology, vol. 14, no. 3, pp. 324-335 (1996).
315. G. Bendelli, M. Burzio, M. Calzavara, P. Cinato, P. Gambini, M. Puleo, E.Vezzoni, F. Delorme, and H. Nakajima, "PhotonicATMswitch based on a multiwavelength fiber-loop buffer," in Proc. OFC'95, San Diego, California, pp. 141-142 (Feb. 1995).
316. Y. Yamada, K. Sasayama, and K. Habara, "Transparent optical-loop memory for optical FDM packet buffering with differential receiver," in Proc. ECOC'96, Olsa, Norway, pp. 317-320 (Sept. 1996).
317. J. Ramamirtham and J. Turner, "Time sliced optical burst switching," in Proc. IEEE INFOCOM'03, San Francisco, California, pp. 2030-2038 (Apr. 2003).
318. M. C. Chia, D. K. Hunter, I. Andonovic, P. Ball, I. Wright, S. P. Ferguson, K. M. Guild, and M. J. O. Mahony, "Packet loss and delay performance of feedback and feed-forward arrayedwaveguide gratings-based optical packet switches with WDM inputs-outputs," IEEE/OSA Journal of Lightwave Technology, vol. 19, no. 9, pp. 1241-1254 (Sept. 2001).
319. C. Qiao and M.Yoo, "Optical burst switching (OBS) -A new paradigm for an optical Internet," Journal of High Speed Networks, vol. 8, no. 1, pp. 69-84 (1999).
320. I. Baldine, G. N. Rouskas, H. G. Perros, and D. Stevenson, "Jumpstart: a just-in-time signaling architecture for WDM burst-switched networks," IEEE Communications Magazine, vol. 40, no. 2, pp. 82-89 (Feb. 2002).
321. M. J. Karol, "Shared-memory optical packet (ATM) switch," Multigigabit Fiber Communications Systems, vol. 2024, pp. 212-222 (July 1993).
322. S. Y. Liew, G. Hu, and H. J. Chao, "Scheduling algorithms for shared fiber-delay-line optical packet switches. Part I: The single-stage case," IEEE Journal of Lightwave Technology, vol. 23, issue. 4, pp. 1586-1600 (Apr. 2005).
323. N. Huang, G. Liaw, and C. Wang, "A novel all-optical transport network with time-shared wavelength channels," IEEE Journal on Selected Areas in Communications, vol. 18, no. 10, pp. 1863-1875 (Oct. 2000).
324. B.Wen and K. M. Sivalingam, "Routing, wavelength and time-slot assignment in time division multiplexed wavelength-routed optical WDM networks," in Proc. IEEE INFOCOM'02, New York, NewYork, vol. 3, pp. 1442-1450 (Apr. 2002).
325. R. Srinivasan and A. K. Somani, "A generalized framework for analyzing time-space switched optical networks," in Proc. IEEE INFOCOM'01, Anchorage, Alaska, pp. 179-188 (Apr. 2001).
326. S. Jiang, G. Hu, S.Y. Liew, and H. J. Chao, "Scheduling algorithms for shared fiber-delay-line optical packet switches, Part II: The 3-stage Clos-Network case," IEEE Journal of Lightwave Technology, vol. 23, issue. 4, pp. 1601-1609 (Apr. 2005).
327. C. Clos, "A study of non-blocking switching networks," Bell System Technical Journal, vol. 32, no. 3, pp. 406-424 (Mar. 1953).
328. Y. S.Yeh, M. G. Hluchyj, and A. S. Acampora, "The knockout switch: a simple, modular architecture for high-performance switching," IEEE Journal on Selected Areas in Communications, vol. 5, no. 8, pp. 1274-1283 (Oct. 1987).
329. The Challenge for Next Generation Network Processors, Agere Inc., Apr. 2001, white paper.
330. N. Shah, "Understanding network processors," Master's thesis, University of California, Berkeley, Sept. 2001, Master Degree Dissertation.
331. "Network processing forum." [Online]. Available at: http://www.npforum.org/.
332. J. M. Rabeay, M. Potkonjak, F. Koushanfar, S.-F. Li, and T. Tuan, "Challenges and opportunities in broadband and wireless communication designs," in Proc. IEEE/ACM International Conference on Computer Aided Design, San Jose, California, pp. 76-82 (Nov. 2000).
333. Intel Internet Exchange Architecture Network Processors Flexible,Wire-Speed Processing from the Customer Premises to the Network Core, Intel Inc., 2002, white paper.
334. Network Processors: Why? What? When?, Silicon Access Inc., July 2002, presentation.
335. Network Processor Designs for Next-Generation Networking Equipment, EZchip Inc., Dec. 1999, white paper.
336. X. Nie, L. Gazsi, F. Engel, and G. Fettweis, "A new network processor architecture for highspeed communications," in Proc. IEEEWorkshop on Signal Processing Systems, Taipei, China, pp. 548-557 (Oct. 1999).
337. T.Wolf and M. Frankly, "CommBench-A telecommunication benchmark for network processors," in Proc. IEEE International Symposium on Performance Analysis of Systems and Software, Austin, Texas, pp. 154-162 (Apr. 2000).
338. H. Liu, "Atrace driven study of packet level parallelism," in Proc. IEEE International Conference on Communications, NewYork, NewYork, vol. 4, pp. 2191-2195 (Apr. 2002).
339. P. Crowley, M. E. Fiuczynski, J.-L. Baer, and B. N. Bershad, "Characterizing processor architectures for programmable network interface," in Proc. International Conference on Supercomputing, Santa Fe, New Mexico, pp. 54-65 (May 2000).
340. W. Bux, W. E. Denzel, T. Engbersen, A. Herkersdort, and R. P. Luijten, "Technologies and building blocks for fast packet forwarding," IEEE Communications Magazine, vol. 39, issue. 1, pp. 70-77 (Jan. 2001).
341. Challenges in Designing 40-Gigabit Network Processors, EZchip Inc., Dec. 2001, white paper.
342. NP-1: Reducing Router Chip-Count, Power and Cost by 80%, EZchip Inc., June 2002, white paper.
343. D. A. Patterson and J. L. Hennyssy, Computer Architecture: A Quantitative Approach, 3rd ed. Morgan Kaufmann, San Francisco, California, 2003.
344. PowerNP NP4GS3 Network Processor Data Sheet, IBM Inc., Feb. 2002.
345. B. Klein and J. Garza, "Agere systems-communications optimized payload plus network processor architecture," in Network Processor Design: Issues and Practices. Morgan Kaufmann, San Francisco, California, 2002, vol. 1, pp. 219-233.
346. Intel IXP2800 Network Processor-For OC-192/10 Gbps network edge and core applications, Intel Inc., product brief.
347. J. Marshall, "Cisco systems-Toaster2," in Network Processor Design: Issues and Practices. Morgan Kaufmann, San Francisco, California, 2002, vol. 1, pp. 235-248.
348. Implementing a Flexible Hardware-based Router for the New IP Infrastructure, Juniper Inc., white paper.
349. LA-1 interface. [Online]. Available at: http://www.npforum.org/ApprovedSpecs.htm
350. H. Bhugra, LA-1: Examining the Look-Aside Processor Interface. [Online]. Available at: http://www.commsdesign.com/
351. M. J. Miller, "IDT network search engine with QDR LA-1 interface," in Network Processor Design, Issues and Practices. Morgan Kaufmann, San Francisco, California, 2003, vol. 2, pp. 365-384.
352. 4.5M and 9M Network Search Engine (NSE) with QDR Interface, Data Sheet, IDT, 2002.
353. Network Search Engine (NSE) TCAM with QDR Interface, User's Manual, IDT, 2002.
354. PAX.port 2500, Data Sheet, IDT, 2003.
355. PAX.port 2500, Technical Summary, IDT, 2003.
356. R. T.Vineet Dujari and A. Shelat, "PMC-Sierra, Inc.-ClassiPI," in Network Processor Design, Issues and Practices. Morgan Kaufmann, San Francisco, California, 2002, vol. 1, pp. 291-305.
357. PM2329 ClassiPI Network Classification Processor Datasheet, PMC-Sierra, Inc., 2001.
358. Technical Guide to the TM10-Preliminary Data Book, Agere System Inc., Dec. 2002.
359. Technical Guide to the APP550 and APP530 Network Processors, Version 7, Agere System Inc., May 2003.
360. Technical Guide to the APP540/520 Network Processors, Version 1, Agere System Inc., May 2003.
361. ZTM Advanced Traffic Manager Product Brief, ZettaCom Inc., May 2004.
362. ZTM552 Traffic Manager Preliminary Data Sheet, version 3.0, ZettaCom Inc., Dec. 2003.
363. ZTM552 Traffic Management Training, ZettaCom Inc., May 2004.
364. Vitesse. [Online]. Available at: http://www.vitesse.com
365. VSC870 datasheet Rev 4.0: high performance serial backplane transceiver, Vitesse. [Online]. Available at: http://www.vitesse.com
366. VSC880 datasheet Rev 4.0: high performance 16 × 16 serial crosspoint switch,Vitesse. [Online]. Available at: http://www.vitesse.com
367. GigaStream intelligent switch fabric VSC872/VSC882 design manual Rev 2.2,Vitesse. [Online]. Available at: http://www.vitesse.com
368. TeraStream intelligent switch fabric VSC871/VSC881 design manual Rev 1.0,Vitesse. [Online]. Available at: http://www.vitesse.com
369. Cyclone Switch Fabric S8505-S8905 Product Concept, Rev0.07, AMCC.
370. PowerPRS Q-64G Packet Routing Switch datasheet, initial release, IBM.
371. Technical Guide to the Pi40X, Rev 18, Agere System Inc., Mar. 2003.
372. Technical Guide to the Pi40C, Rev 13, Agere System Inc., Mar. 2003.
373. Technical Guide to the Pi40SAX and Pi20SAX, Rev 12, Agere System Inc., Sept. 2003.