A pipelined maximal-sized matching scheme for high-speed input-buffered switches

IEICE Transactions on Communications

Volumn E85-B, Issue 7, 2002, Pages 1302-1311

  Oki, Eiji ^a,b   Rojas Cessa, Roberto ^b   Chao, H Jonathan ^b  

^a NTT Network Innovation Laboratories   (Japan)

^b POLYTECHNIC UNIVERSITY   (United States)

Author keywords

Input buffered switch; Maximal sized matching; Pipeline; Scheduling

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; PERFORMANCE; SCHEDULING; TELECOMMUNICATION TRAFFIC;

INPUT-BUFFERED SWITCHES; ITERATIVE DUAL ROUND ROBIN MATCHING; PIPELINED MAXIMAL-SIZED MATCHING SCHEME; VIRTUAL OUTPUT QUEUE;

SWITCHING SYSTEMS;

EID: 0036664504     PISSN: 09168516     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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