Towards simple, high-performance schedulers for high-aggregate bandwidth switches

Proceedings - IEEE INFOCOM

Volumn 3, Issue , 2002, Pages 1160-1169

  Giaccone, Paolo ^a   Prabhakar, Balaji ^b   Shah, Devavrat ^b  

^a POLITECNICO DI TORINO   (Italy)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; FREQUENCY ALLOCATION; GRAPH THEORY; PACKET SWITCHING; PARALLEL PROCESSING SYSTEMS; QUEUEING NETWORKS; RANDOM PROCESSES; THEOREM PROVING;

HIGH AGGREGATE BANDWIDTH SWITCHES; INPUT QUEUED SWITCH; MAXIMUM WEIGHT MATCHING ALGORITHM; VIRTUAL OUTPUT QUEUE;

CONGESTION CONTROL (COMMUNICATION);

EID: 0036349563     PISSN: 0743166X     EISSN: None     Source Type: Journal    
DOI: 10.1109/INFCOM.2002.1019366     Document Type: Article

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