Low-cost scalable switching solutions for broadband networking: The ATLANTA architecture and chipset

IEEE Communications Magazine

Volumn 35, Issue 12, 1997, Pages 44-53

  Chiussi, Fabio M ^a,b,c,d,e   Kneuer, Joseph G ^a,f,g,h,i   Kumar, Vijay P ^a,j,k,l  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF PADOVA   (Italy)

^c STANFORD UNIVERSITY   (United States)

^d Telettra   (Italy)

^e High Speed Networks Res Department

^f UNIVERSITY OF NOTRE DAME   (United States)

^g SYRACUSE UNIVERSITY   (United States)

^h Space and Naval Warfare Systems Center Pacific   (United States)

ⁱ ATLANTA Design Team   (United States)

^j NOKIA RESEARCH CENTER   (United States)

^k OSMANIA UNIVERSITY   (India)

^l UNIVERSITY OF IOWA   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BROADBAND NETWORKS; BUFFER STORAGE; CONGESTION CONTROL (COMMUNICATION); INTERFACES (COMPUTER); NETWORK PROTOCOLS; STORAGE ALLOCATION (COMPUTER); SWITCHING NETWORKS;

INTERNET PROTOCOL (IP);

SWITCHING SYSTEMS;

EID: 0031337497     PISSN: 01636804     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCOM.1997.642833     Document Type: Article

References (10)

1. T. Kozaki et al., "32 x 32 Shared Buffer Type ATM Switch VLSIs for B-ISDNs," IEEE JSAC, SAC-9, Oct. 1991, pp. 1239-47.
2. Y. Shobatake et al., "A One-Chip Scalable 8x8 ATM Switch LSI Employing Shared Buffer Architecture," IEEE JSAC, SAC-9, Oct. 1991, pp. 1248-54.
3. H. Kuwahara et al., "A Shared Buffer Memory Switch for an ATM Exchange," Proc. ICC '89, paper 4.4, Boston, MA, June 1989.
4. N. Endo et al., "Traffic Characteristics Evaluation of a Shared Buffer ATM Switch," Proc. GLOBECOM '90, paper 905.1, San Diego, CA, Dec. 1990.
5. F. M. Chiussi, Y. Xia, and V. P. Kumar, "Backpressure in Shared-Memory-Based ATM Switches Under Multiplexed Bursty Sources," Proc. INFOCOM '96, San Francisco, CA, Mar. 1996, pp. 830-43.
6. F. M. Chiussi, "Design, Performance, and Implementation of a Three-Stage Banyan-Based Architecture with Input and Output Buffers for Large Fast Packet Switches," Tech. Rep. CSL-TR-93-573, Stanford Univ., Stanford, CA, June 1993.
7. ATM Forum Traffic Management Specification, v. 4.0, Apr. 1996.
8. M. J. Karol and K. Y. Eng, "Performance of Hierarchical Multiplexing in ATM Switch Design," Proc. ICC '92, Chicago, IL, June 1992, pp. 269-75.
9. A. K. Choudhury and E. L. Hahne, "Dynamic Queue Length Thresholds in a Shared Memory ATM Switch," Proc. INFOCOM '96, San Francisco, CA, Mar. 1996.
10. F. M. Chiussi, Y. Xia, and V. P. Kumar, "Performance of Shared-Memory Switches Under Multicast Bursty Traffic," IEEE JSAC, Apr. 1997, pp. 473-86.