Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects

IEEE Transactions on Computers

Volumn 62, Issue 12, 2013, Pages 2382-2396

  Deb, Sujay ^a   Chang, Kevin ^b   Yu, Xinmin ^b   Sah, Suman Prasad ^b   Cosic, Miralem ^b   Ganguly, Amlan ^c   Pande, Partha Pratim ^b   Belzer, Benjamin ^b   Heo, Deukhyoun ^b  

^a INDRAPRASTHA INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b Washington State University   (United States)

^c Rochester Institute of Technology   (United States)

Author keywords

Millimeter wave wireless; Network on chip; Optimization; Performance evaluation; Small world

Indexed keywords

COMMUNICATION INFRASTRUCTURE; ENABLING TECHNOLOGIES; MILLIMETER (MM)-WAVE; NETWORK ON CHIP; NOC ARCHITECTURES; PERFORMANCE EVALUATION; SMALL WORLDS; WIRELESS INTERCONNECTS;

DESIGN; ELECTRONIC DATA INTERCHANGE; ENERGY EFFICIENCY; OPTIMIZATION; SERVERS; VLSI CIRCUITS;

MILLIMETER WAVES;

EID: 84887916468     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.224     Document Type: Article

References (49)

1. D.J. Watts, Small Worlds: The Dynamics of Networks between Order and Randomness, p. 262, Princeton Univ. Press, 1999.
2. B. Razavi, "Design of Millimeter-Wave CMOS Radios: A Tutorial," IEEE Trans. Circuits and Systems I, vol. 56, no. 1, pp. 4-16, Nov. 2009.
3. M.F. Chang et al., "RF Interconnects for Communications On-Chip," Proc. Int'l Symp. Physical Design, pp. 78-83, Apr. 2008.
4. A. Ganguly et al., "Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems," IEEE Trans. Computers, vol. 60, no. 10, pp. 1485-1502, Oct. 2011.
5. R. Marculescu et al., "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, Jan. 2009.
6. U.Y. Ogras and R. Marculescu, "Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD), pp. 246-253, Nov, 2005.
7. U.Y. Ogras and R. Marculescu, "'It's a Small World after All,' NoC Performance Optimization via Long-Range Link Insertion," IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 7, pp. 693-706, July 2006.
8. A. Kumar et al., "Toward Ideal On-Chip Communication Using Express Virtual Channels," IEEE Micro, vol. 28, no. 1, pp. 80-90, Jan./Feb. 2008.
9. T. Krishna et al., "NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication," Proc. IEEE Symp. High Performance Interconnects (HOTI '08), pp. 11-20, Aug. 2008.
10. K. Chang et al., "Performance Evaluation and Design Trade-Offs for Wireless Network-on-Chip Architectures," ACM J. Emerging Technologies in Computing Systems, vol. 8, no. 3, article 23, Aug. 2012.
11. A. Shacham et al., "Photonic Network-on-Chip for Future Generations of Chip Multi-Processors," IEEE Trans. Computers, vol. 57, no. 9, pp. 1246-1260, Sept. 2008.
12. I. O'Connor et al., "Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect," IEEE Trans. Very Large Scale Integration Systems, vol. 15, no. 8, pp. 927-940, Aug. 2007.
13. D. Vantrease et al., "Corona: System Implications of Emerging Nanophotonic Technology," Proc. IEEE Int'l Symp. Computer Architecture (ISCA '08), pp. 153-164, June, 2008.
14. M.F. Chang et al., "CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect," Proc. IEEE Int'l Symp. High-Performance Computer Architecture (HPCA '08), pp. 191-202, Feb. 2008.
15. D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip," IEEE Trans. Computers, vol. 57, no. 9, pp. 1230-1245, Sept. 2008.
16. D. Zhao and R. Wu, "Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip," Proc. IEEE/ ACM Int'l Symp. Networks-on-Chip, pp. 27-34, May 2012.
17. D. Zhao et al., "Design of Multi-Channel Wireless NoC to Improve on-Chip Communication Capacity" Proc. ACM/IEEE Fifth Int'l Symp. Networks-on-Chip, pp. 177-184, 2011.
18. J. Lin et al., "Communication Using Antennas Fabricated in Silicon Integrated Circuits," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1678-1687, Aug. 2007.
19. Y.P. Zhang et al., "Propagation Mechanisms of Radio Waves over Intra-Chip Channels with Integrated Antennas: Frequency-Domain Measurements and Time-Domain Analysis," IEEE Trans. Antennas and Propagation, vol. 55, no. 10, pp. 2900-2906. Oct. 2007.
20. E. Seok and K.O. Kenneth, "Design Rules for Improving Predictability of on-Chip Antenna Characteristics in the Presence of Other Metal Structures," Proc. IEEE Int'l Interconnect Technology Conf., pp. 120-122, June 2005.
21. J. Branch et al., "Wireless Communication in a Flip-Chip Package Using Integrated Antennas on Silicon Substrates," IEEE Electron Device Letters, vol. 26, no. 2, pp 115-117, Feb. 2005.
22. J. Mehta "Switching Noise of Integrated Circuits (IC's) Picked up by a Planar Dipole Antenna Mounted Near the IC's," IEEE Trans. Electro-Magnetic Compatibility, vol. 44, no. 5, pp. 282-290, May 2002.
23. S.B. Lee et al., "A Scalable Micro Wireless Interconnect Structure for CMPs," Proc. ACM MobiCom, pp. 217-228, Sept. 2009.
24. D. DiTomaso et al., "iWise: Inter-Router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture," Proc. Ann. Symp. High Performance Interconnects (HOTI '11), pp. 11-18, 2011.
25. D.J. Watts and S.H. Strogatz, "Collective Dynamics of 'Small-World' Networks," Nature, vol. 393, pp. 440-442, 1998.
26. M. Buchanan, Nexus: Small Worlds and the Groundbreaking Theory of Networks. W.W. Norton & Company, 2003.
27. C. Teuscher, "Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs," Chaos, vol. 17, no. 2, article 026106, 2007.
28. T. Petermann and P. De Los Rios, "Physical Realizability of Small-World Networks," Physical Rev. E, vol. 73, article 026114, 2006.
29. S. Kirkpatrick et al., "Optimization by Simulated Annealing," Science, vol. 220, pp. 671-680, 1983.
30. E.W. Dijkstra, "A Note on Two Problems in Connexion with Graphs," Numerische Mathematik, vol. 1, pp. 269-271, 1959.
31. S. Deb, Multi-Objective Optimization Using Evolutionary Algorithms. John Wiley & Sons, 2001.
32. A.E. Eiben and J.E. Smith, Introduction to Evolutionary Computing. Springer-Verlag, 2003.
33. M. Sipper, Evolution of Parallel Cellular Machines: The Cellular Programming Approach. Springer-Verlag, 1997.
34. T. Jansen and I. Wegener, "A Comparison of Simulated Annealing with a Simple Evolutionary Algorithm on Pseudo-Boolean Functions of Unitation," Theoretical Computer Science, vol. 386, pp. 73-93, 2007.
35. B.A. Floyd et al., "Intra-Chip Wireless Interconnect for Clock Distribution Implemented with Integrated Antennas, Receivers, and Transmitters," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
36. M.J. Deen and O. Marinov, "Effect of Forward and Reverse Substrate Biasing on Low-Frequency Noise in Silicon PMOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 409-413, Mar. 2002.
37. G. Kathiresan and C. Toumazou, "A Low Voltage Bulk Driven Down-Conversion Mixer Core," Proc. IEEE Int'l Symp. Circuit and Systems, vol. 2, pp. 598-601, 1999.
38. X. Yu et al., "A Wideband Body-Enabled Millimeter-Wave Transceiver for Wireless Network-on-Chip," Proc. IEEE 54th Midwest Symp. Circuits and Systems pp. 1-4, 2011.
39. J. Duato et al., Interconnection Networks - An Engineering Approach. Morgan Kaufmann, 2002.
40. J. Draper et al., "Routing in Bidirectional k-ary n-Cube Switch the Red Rover Algorithm," Proc. Int'l Conf. Parallel and Distributed Processing Techniques and Applications, pp. 1184-1193, 1997.
41. A. Kumar et al., "Token Flow Control," Proc. IEEE/ACM 41st Int'l Symp. Microarchitecture (MICRO-41), pp. 1184-1193, 2008.
42. W. Stallings, Data and Computer Communications. Prentice Hall 2007.
43. R. Holsmark et al., "HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip," Proc. Int'l Symp. Network-on-Chip, 2009.
44. Agilent Technologies, "Homepage," http://agilent.com, 2013.
45. Taiwan Semiconductor Manufacturing Company, "Homepage," http://www.tsmc.com/english/default.htm, 2013.
46. P.P. Pande et al., "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
47. X. Yu et al., "Performance Evaluation and Receiver Front-End Design for on-Chip Millimeter-Wave Wireless Interconnect," Proc. IEEE Int'l Green Computing Conf. (IGCC) 2010.
48. S. Deb et al., "Enhancing Performance of Network-on-Chip Architectures with Millimeter-Wave Wireless Interconnects," Proc. IEEE Int'l Conf. Application-Specifics Systems and Processors (ASAP '10), pp. 73-80, 2010.
49. B.G. Lee et al., "Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for on-Chip Networks," IEEE Photonics Technology Letters, vol. 20, no. 6, pp. 398-400, Mar. 2008.