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Volumn , Issue , 2009, Pages 217-228

A scalable micro wireless interconnect structure for CMPs

Author keywords

Chip multiprocessors; On chip wireless interconnection network

Indexed keywords

CHIP MULTIPROCESSOR; DEADLOCK FREE; EMERGING TECHNOLOGIES; IN-CHIP; INTERCONNECT TECHNOLOGY; MESH DESIGNS; MULTIPLE RECEIVE ANTENNAS; ON CHIP ANTENNA; ON CHIP INTERCONNECT; ON CHIPS; SCALABLE PERFORMANCE; SCALING LIMITATION; TERAHERTZ FREQUENCIES; TRANSMIT ANTENNA; WIRELESS INTERCONNECTION; WIRELESS INTERCONNECTS; WIRELESS NETWORKING; WIRELESS ROUTERS;

EID: 70450278756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1614320.1614345     Document Type: Conference Paper
Times cited : (177)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.