Design of multi-channel wireless NoC to improve on-chip communication capacity

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 177-184

  Zhao, Dan ^a   Wang, Yi ^a   Li, Jian ^b   Kikkawa, Takamaro ^c  

^a Informatics Research Institute   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP DESIGN; CHIP-LEVEL; COMMUNICATION BANDWIDTH; COMPUTING PERFORMANCE; EFFICIENT CHANNELS; END-TO-END LATENCY; EXPONENTIAL GROWTH; FLEXIBLE TOPOLOGY; HIGH BANDWIDTH; LOCATION-BASED ROUTING SCHEMES; LOW COSTS; LOW LATENCY; MANY-CORE; MILLIMETER RANGE; MULTI HOP COMMUNICATION; MULTI-CHANNEL; ON CHIP COMMUNICATION; ON-CHIP INTERCONNECTION NETWORK; PERFORMANCE IMPROVEMENTS; TRAFFIC PATTERN; WIRELESS NETWORK-ON-CHIP;

BANDWIDTH; COMMUNICATION; DESIGN; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PACKET NETWORKS; ULTRA-WIDEBAND (UWB); VLSI CIRCUITS; WIRELESS SENSOR NETWORKS;

TELECOMMUNICATION SYSTEMS;

EID: 79960326675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999975     Document Type: Conference Paper

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