Meeting midway: Improving CMP performance with memory-side prefetching

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2013, Pages 289-298

  Yedlapalli, Praveen ^a   Kotra, Jagadish ^a   Kultursay, Emre ^a   Kandemir, Mahmut ^a   Das, Chita R ^a   Sivasubramaniam, Anand ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

CMP; DRAM; memory prefetching; NOC

Indexed keywords

CHIP MULTIPROCESSOR; CMP; MEMORY CHANNELS; MEMORY CONTROLLER; MULTITHREADED; NOC; PREFETCHING; RESOURCE CONTENTION;

DYNAMIC RANDOM ACCESS STORAGE; KNOWLEDGE MANAGEMENT; MULTIPROGRAMMING; PARALLEL ARCHITECTURES;

CACHE MEMORY;

EID: 84887501415     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2013.6618825     Document Type: Conference Paper

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