Memory-side prefetching for linked data structures for processor-in-memory systems

Journal of Parallel and Distributed Computing

Volumn 65, Issue 4, 2005, Pages 448-463

  Hughes, Christopher J ^a   Adve, Sarita V ^b  

^a INTEL CORPORATION   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Linked data structures; Prefetching; Processor in memory

Indexed keywords

CACHE MEMORY; COMPUTER SOFTWARE; DATA TRANSFER; ENCODING (SYMBOLS); OBJECT ORIENTED PROGRAMMING; PROGRAM PROCESSORS; SEARCH ENGINES;

LINKED DATA STRUCTURES (LDS); MEMORY LATENCY; PREFETCHING; PROCESSOR-IN-MEMORY;

DATA STRUCTURES;

EID: 14944355925     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2004.11.004     Document Type: Article

References (41)

1. T. Alexander, G. Kedem, Distributed prefetch-buffer/cache design for high performance memory systems, in: Proceedings of the Second International Symposium on High-Performance Computer Archives, 1996.
2. M. Bekerman, et al., Correlated load-address predictors, in: Proceedings of the 26th International Symposium on Computer Archives, 1999.
3. D. Burger, S. Kaxiras, J.R. Goodman, DataScalar architectures, in: Proceedings of the 24th International Symposium on Computer Archives, 1997.
4. B. Calder, C. Krintz, S. John, T. Austin, Cache-conscious data placement, in: Proceedings of the Eighth International Conference on Archives Support for Programming Languages and Operating Systems, 1998.
5. M.C. Carlisle, A. Rogers, Software caching and computation migration in Olden, in: Proceedings of the Sixth Principles and Practice of Parallel Programming, 1995.
6. J. Carter, W. Hsieh, L. Stoller, M. Swanson, L. Zhang, Impulse: building a smarter memory controller, in: Proceedings of the Fifth International Symposium on High-Performance Computer Archives, 1999.
7. T.-F. Chen, An effective programmable prefetch engine for on-chip caches, in: Proceedings of the 28th International Symposium on Microarchives, 1995.
8. T.-F. Chen, J.-L. Baer, Effective hardware-based data prefetching for high-performance processors, IEEE Trans. Comput. (1995).
9. T.M. Chilimbi, M.D. Hill, J.R. Larus, Cache-conscious structure layout, in: Proceedings of the SIGPLAN'99 Conference on Programming Language Design and Implementation, 1999.
10. D.G. Elliot, W.M. Snelgrove, Computational ram: a memory-SIMD hybrid and its application to DSP, in: Proceedings of the Custom Integrated Circuits Conference, 1992.
11. M. Gokhale, B. Holmes, K. Iobst, Processing in memory: the terasys massively parallel PIM array, IEEE Comput. (April 1995).
12. M. Hall, et al., Mapping irregular applications to DIVA, a PIM-based data-intensive architecture, in: Proceedings of Supercomputing'99, 1999.
13. C.J. Hughes, Prefetching linked data structures in systems with merged DRAM-logic, Master's Thesis, University of Illinois at Urbana-Champaign, May 2000, URL: http://rsim.cs.uiuc.edu/c̃jhughes/cjhughesmsthesis.pdf.
14. C.J. Hughes, S. Adve, Supplemental data for memory-side prefetching for linked data structures, URL: http://rsim.cs.uiuc.edu/c̃jhughes/alternative- arch.ps.
15. IBM, URL: http://www.research.ibm.com/bluegene/comsci.html.
16. Intel, Intel IA-64 Architecture Software Developer's Manual, 2000.
17. Intel, IA-32 Intel Architecture Software Developer's Manual, 2001.
18. B.L. Jacob, T.N. Mudge, A look at several memory management units, TLB-refill mechanisms, and page table organizations, in: Proceedings of the Eighth International Conference on Archives Support for Programming Languages and Operating Systems, 1998.
19. D. Joseph, D. Grunwald, Prefetching using Markov predictors, in: Proceedings of the 24th International Symposium on Computer Archives, 1997.
20. Y. Kang, et al., FlexRAM: toward an advanced intelligent memory system, in: Proceedings of the 1999 International Conference on Computer Design, 1999.
21. M. Karlsson, F. Dahlgren, P. Stenström, A prefetching technique for irregular accesses to linked data structures, in: Proceedings of the Sixth International Symposium on High-Performance Computer Archives, 2000.
22. P.M. Kogge, The EXECUBE approach to massively parallel processing, in: Proceedings of the 1994 International Conference on Parallel Proceedings, 1994.
23. N. Kohout, S. Choi, D. Yeung, Multi-chain prefetching: exploiting natural memory parallelism in pointer-chasing codes, Technical Report UMD-SCA-TR-2000-01, University of Maryland at College Park, 2000.
24. C.E. Kozyrakis, S. Perissakis, D. Patterson, T. Anderson, K. Asanović, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R. Thomas, N. Treuhaft, K. Yelick, Scalable processors in the billion-transistor era: IRAM, IEEE Comput. (September 1997).
25. D. Kroft, Lockup-free instruction fetch/prefetch cache organization, in: Proceedings of Eighth Symposium on Computer Archives, May 1981, pp. 81-87.
26. M.H. Lipasti, W.J. Schmidt, S.R. Kunkel, R.R. Roediger, SPAID: software prefetching in pointer- and call-intensive environments, in: Proceedings of the 28th International Symposium on Microarchives, 1995.
27. C.-K. Luk, T.C. Mowry, Compiler-based prefetching for recursive data structures, in: Proceedings of the Seventh International Conference on Archives Support for Programming Languages and Operating Systems, 1996.
28. C.-K. Luk, T.C. Mowry, Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation, in: Proceedings of the 26th International Symposium on Computer Archives, 1999.
29. S. Mehrotra, L. Harrison, Examination of a memory access classification scheme for pointer-intensive and numeric programs, in: Proceedings of the 10th International Conference on Supercomputing, 1996.
30. T.C. Mowry, M.S. Lam, A. Gupta, Design and evaluation of a compiler algorithm for prefetching, in: Proceedings of the Fifth International Conference on Archives Support for Programming Languages and Operating Systems, 1992.
31. M. Oskin, F.T. Chong, T. Sherwood, Active pages: a computation model for intelligent memory, in: Proceedings of the 25th International Symposium on Computer Archives, 1998.
32. V.S. Pai, P. Ranganathan, H. Abdel-Shafi, S. Adve, The impact of exploiting instruction-level parallelism on shared-memory multiprocessors, IEEE Trans. Comput. (special issue on caches) (February 1999).
33. V.S. Pai, P. Ranganathan, S.V. Adve, RSIM Reference Manual version 1.0, Technical Report 9705, Department of Electronics and Computer Engineering, Rice University, August 1997.
34. S.S. Pinter, A. Yoaz, Tango: a hardware-based data prefetching technique for superscalar processors, in: Proceedings of the 29th International Symposium on Microarchives, 1996.
35. A. Roth, A. Moshovos, G.S. Sohi, Dependence based prefetching for linked data structures, in: Proceedings of the Eighth International Conference on Archives Support for Programming Languages and Operating Systems, 1998.
36. A. Roth, G.S. Sohi, Effective jump-pointer prefetching for linked data structures, in: Proceedings of the 26th International Symposium on Computer Archives, 1999.
37. A. Saulsbury, F. Pong, A. Nowatzyk, Missing the memory wall: the case for processor/memory integration, in: Proceedings of the 23th International Symposium on Computer Archives, 1996.
38. S. Wallach, Billions and billions, Fourth International Symposium on High-Performance Computer Archives, 1998, Keynote address.
39. S.C. Woo, et al., The SPLASH-2 programs: characterization and methodological considerations, in: Proceedings of the 22nd International Symposium on Computer Archives, June 1995, pp. 24-36.
40. C.-L. Yang, A.R. Lebeck, Push vs. pull: data movement for linked data structures, in: Proceedings of the 2000 International Conference on Supercomputing, May 2000.
41. Z. Zhang, J. Torrellas, Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching, in: Proceedings of the 22nd International Symposium on Computer Archives, 1995.