A prefetching technique for irregular accesses to linked data structures

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2000, Pages 206-217

  Karlsson, Magnus ^a   Dahlgren, Fredrik ^b   Stenström, Per ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^b ERICSSON RESEARCH   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STRUCTURES; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIME SERIES ANALYSIS; TREES (MATHEMATICS);

BINARY TREES; LINKED DATA STRUCTURES; PREFETCHING TECHNIQUE;

DATA FLOW ANALYSIS;

EID: 0034581346     PISSN: 15300897     EISSN: None     Source Type: Journal    
DOI: 10.1109/HPCA.2000.824351     Document Type: Article

References (20)

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12. Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps