Balancing locality and parallelism on shared-cache mulit-core systems

2009 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009

Volumn , Issue , 2009, Pages 188-195

  Cade, Michael Jason ^a   Qasem, Apan ^a  

^a TEXAS STATE UNIVERSITY   (United States)

Author keywords

Memory hierarchy optimization; Parallelism; Performance tuning; Shared cache

Indexed keywords

CONCURRENT THREADS; CORE SYSTEMS; DATA LOCALITY; DATA REUSE; HARDWARE FEATURES; MEMORY HIERARCHY OPTIMIZATION; MULTI-CORE SYSTEMS; MULTICORE ARCHITECTURES; NEW OPPORTUNITIES; NUMBER OF THREADS; PARALLELISM; PERFORMANCE CAPABILITY; PERFORMANCE ENHANCING; PERFORMANCE OPTIMIZATIONS; PERFORMANCE POTENTIALS; PERFORMANCE TUNING; PROCESSING UNITS; SHARED-CACHE; STATE OF THE ART; THREAD LEVEL PARALLELISM;

COMPUTER SCIENCE; MICROPROCESSOR CHIPS; PROFITABILITY; SOFTWARE ARCHITECTURE; SYNCHRONIZATION; TUNING; WINDOWS;

CACHE MEMORY;

EID: 70449562109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCC.2009.61     Document Type: Conference Paper

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