Cost-effective compiler directed memory prefetching and bypassing

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 189-198

  Ortega, D ^a   Ayguade E ^a   Baer, J L ^b   Valero, M ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b University of Washington   (United States)

Author keywords

Application software; Bridges; Costs; Delay; Hardware; Pipelines; Prefetching; Process design; Proposals; Registers

Indexed keywords

APPLICATION PROGRAMS; BENCHMARKING; BRIDGES; COMPUTER HARDWARE; COST EFFECTIVENESS; COSTS; HARDWARE; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PIPELINES; PROCESS DESIGN;

DELAY; HYBRID IMPLEMENTATION; NUMERICAL APPLICATIONS; PREFETCHING; PREFETCHING TECHNIQUES; PROPOSALS; REGISTERS; SOFTWARE AND HARDWARES;

MEMORY ARCHITECTURE;

EID: 33644639438     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106017     Document Type: Conference Paper

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