Application-specific network-on-chip synthesis with flexible router placement

Journal of Systems Architecture

Volumn 59, Issue 7, 2013, Pages 361-371

  Soumya, J ^a   Chattopadhyay, Santanu ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Application specific network on chip; Communication cost; Integer linear programming; Particle swarm optimization

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; COST REDUCTION; COSTS; DISTRIBUTED COMPUTER SYSTEMS; ENERGY UTILIZATION; HEURISTIC METHODS; INTEGER PROGRAMMING; MESH GENERATION; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; OPTIMIZATION; PARTICLE SWARM OPTIMIZATION (PSO); PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; SERVERS; SYSTEM-ON-CHIP; TOPOLOGY;

APPLICATION SPECIFIC NETWORK ON CHIP; COMMUNICATION COST; COMMUNICATION PROBLEMS; INTEGER LINEAR PROGRAMMING; INTEGER LINEAR PROGRAMMING FORMULATION; MULTI PROCESSOR SYSTEM ON CHIPS; NETWORK-ON-CHIP(NOC); OPTIMIZED APPLICATION;

INTEGRATED CIRCUIT DESIGN;

EID: 84886097408     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2013.05.013     Document Type: Article

References (46)

1. W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of the Design Automation Conference, 2001, pp. 684-689. (Pubitemid 32841038)
2. Jingcao Hu, R. Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, in: Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference, 21-24 January, 2003, pp. 233-239.
3. S. Murali, G. De Micheli, Bandwidth constrained mapping of cores onto NoC architectures, in: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, vol. 2, February 2004, pp. 896-901.
4. G. Ascia, V. Catania, M. Palesi, Multi-objective mapping for mesh-based NoC architectures, in: CODES + ISSS 2004. International Conference on Hardware/Software Codesign and System Synthesis, 8-10 Sept. 2004, pp. 182-187. (Pubitemid 40457625)
5. L. Benini, Application Specific NoC Design, in: Proceedings of the Design, Automation and Test in Europe, vol. 1, 6-10 March, 2006, pp. 1-5.
6. W.E. Donath, Complexity theory and design automation, in: Proceedings of the 17th Conference on Design Automation, 23-25 June 1980, pp. 412-419.
7. U.Y. Ogras, R. Marculescu, Application-specific network-on-chip architecture customization via long-range link insertion, in: ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 6-10 November, 2005, pp. 246-253. (Pubitemid 44815723)
8. A. Pinto, L.P. Carloni, A.L. Sangiovanni-Vincentelli, Efficient synthesis of networks on chip, in: Proceedings of the 21st International Conference on Computer Design, 13-15 October, 2003, pp. 146-150.
9. I. Korotkyi, O. Lysenko, Application-specific network-on-chip with link aggregation, in: 2012 Mediterranean Conference on Embedded Computing (MECO), 19-21 June, 2012, pp. 9-12.
10. A.A. Morgan, H. Elmiligi, M.W. El-Kharashi, F. Gebali, Area-aware topology generation for Application-Specific Networks-on-Chip using network partitioning, in: PacRim 2009. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 23-26 August, 2009, pp. 979-984.
11. A. M'zah, O. Hammami, Area/delay driven NoC synthesis, in: 2011 International Conference on Microelectronics (ICM), 19-22 December, 2011, pp. 1-61.
12. A.A. Morgan, H. Elmiligi, M. Watheq El-Kharashi, F. Gebali, Networks-on-Chip topology generation techniques: area and delay evaluation, in: IDT 2008. Third International Conference on Design and Test Workshop, 20-22 December, 2008, pp. 33-38.
13. Sami J. Habib, Mohammad Gh. Mohammad, Q8WARE: synthesis tool for Network-on-Chip applications, in: Innovations in Information Technology, November 2006, pp. 1-5.
14. K. Srinivasan, K.S. Chatha, SAGA: synthesis technique for guaranteed throughput NoC architectures, in: Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, vol. 1, 18-21 January, 2005, pp. 489-494.
15. I. Filippopoulos, I. Anagnostopoulos, A. Bartzas, D. Soudris, G. Economakos, Systematic exploration of energy-efficient Application-Specific Network-on- Chip architectures, in: 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 5-7 July, 2010, pp. 133-138.
16. V. Dumitriu, G.N. Khan, Throughput-oriented NoC topology generation and analysis for high performance SoCs, in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 10, October 2009, pp.1433-1446.
17. Y. Ar, S. Tosun, H. Kaplan, TopGen: a new algorithm for automatic topology generation for Network on Chip architectures to reduce power consumption, in: AICT 2009. International Conference on Application of Information and Communication Technologies, 14-16 October, 2009, pp. 1-5.
18. A. Jalabert, S. Murali, L. Benini, G. De Micheli, pipesCompiler: a tool for instantiating application specific networks on chip, in: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, vol. 2, 16- 20 February, 2004, pp. 884-889.
19. M. Reza Kakoee, F. Angiolin, S. Murali, A. Pullini, C. Seiculescu, L. Benini, A floorplan-aware interactive tool flow for NoC design and synthesis, in: SOCC 2009. Proceedings of IEEE International SOC Conference, 9-11 September, 2009, pp. 379-382.
20. G. Leary, K. Srinivasan, K. Mehta, K.S. Chatha, Design of Network-on-Chip Architectures with a genetic algorithm-based technique, in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, May 2009, pp. 674-687.
21. U.Y. Ogras, R. Marculescu, Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach, in: Proceedings of the Design, Automation and Test in Europe, 7-11 March, 2005, pp. 352-357.
22. Guoming Lai, Xiaola Lin, Siyan Lai, GA-based floorplan-aware topology synthesis of application-specific network-on-chip, in: 2010 IEEE International Conference on Intelligent Computing and Intelligent Systems (ICIS), vol. 2, 29-31 October, 2010, pp. 554-558.
23. A. Tino, G.N. Khan, Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures, in: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 14-18 March, 2011, pp. 1-6.
24. S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, G. De Micheli, pipes Lite: a synthesis oriented design library for networks on chips, in: Proceedings of the Design, Automation and Test in Europe, 7-11 March, 2005, pp. 1188- 1193. (Pubitemid 44172171)
25. T. Ahoen, A. David, H. Bin, J. Nurmi, Topology optimization for application specific networks on chip, in: Proceedings of the International Workshop on System level Interconnect Prediction, February 2004, pp. 53-60.
26. K. Srinivasan, K.S. Chatha, G. Konjevod, An automated technique for topology and route generation of application specific on-chip interconnection networks, in: ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 6-10 November, 2005, pp. 231-237. (Pubitemid 44815721)
27. K. Srinivasan, K.S. Chatha, G. Konjevod, Linear-programming-based techniques for synthesis of network-on-chip architectures, in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, April, 2006, pp. 407-420. (Pubitemid 44143984)
28. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, L. Raffo, Designing Application-Specific Networks on Chips with Floorplan Information, in: ICCAD '06. IEEE/ACM International Conference on Computer-Aided Design, 5-9 November, 2006, pp. 355-362.
29. J. Chan, S. Parameswaran, NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks, in: ASPDAC 2008. Asia and South Pacific Design Automation Conference, 21-24 March, 2008, pp. 265- 270.
30. Bei Yu, Sheqin Dong, Song Chen, S. Goto, Floorplanning and topology generation for application-specific Network-on-Chip, in: 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 18-21 January, 2010, pp. 535-540.
31. Shan Yan, B. Lin, Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees, in: ASPDAC 2008. Asia and South Pacific Design Automation Conference, 21-24 March, 2008, pp. 277-282.
32. Wei Zhong, Bei Yu, Song Chen, T. Yoshimura, Sheqin Dong, S. Goto, Application-specific Network-on-Chip synthesis: cluster generation and network component insertion, in: 12th International Symposium on Quality Electronic Design (ISQED), 14-16 March, 2011, pp. 1-6.
33. D. Bertozzi, A. Jalabert, Srinivasan Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli, NoC synthesis flow for customized domain specific multiprocessor systems-on-chip, in: IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, February 2005,, pp. 113-129. (Pubitemid 40351826)
34. Soohyun Kwon, S. Pasricha, Jeonghun Cho, POSEIDON: a framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors, in: 12th International Symposium on Quality Electronic Design (ISQED), 14-16 March, 2011, pp. 1-7.
35. G.N. Khan, A. Tino, Synthesis of NoC Interconnects for Custom MPSoC Architectures, in: Sixth IEEE/ACM International Symposium on Networks on Chip (NoCS), 9-11 May, 2012, pp. 75-82.
36. www.ibm.com/software/in/integration/optimization/cplex.
37. J. Kennedy, R. Eberhart, Particle swarm optimization, in: Proceedings., IEEE International Conference on Neural Networks, vol. 4, Nov/Dec 1995, pp. 1942- 1948.
38. Kang-Ping Wang, Lan Huang, Chun-Guang Zhou, Wei Pang, Particle swarm optimization for traveling salesman problem, in: International Conference on Machine Learning and Cybernetics, vol. 3, 2-5 November, 2003, pp. 1583- 1585.
39. Luo Guilan, Zhao Hai, Song Chunhe, Convergence analysis of a dynamic discrete PSO algorithm, in: ICINIS '08. First International Conference on Intelligent Networks and Intelligent Systems, 1-3 November, 2008, pp. 89-92.
40. E. Salminen, A. Kulmala, T.D. Hmlinen, Survey of network-on-chip proposals, Tech. Rep, March 2008 [Online]. Available from: .
41. R. Ho, K.W. Mai, M.A. Horowitz, The future of wires, Proceedings of the IEEE 89 (4) (Apr 2001) 490-504. (Pubitemid 33766588)
42. Design Vision User Guide, Version U-2003.03, March 2003, Synopsys, Inc.
43. Santanu Kundu, J. Soumya, Santanu Chattopadhyay, Design and evaluation of Mesh-of-Tree based Network-on Chip using virtual channel router, Microprocessors and Microsystems 36 (6) (2012) 471-488.
44. Primepower Manual, Version Y-2006.06, June 2006, Synopys, Inc.
45. HSPICE Reference Guide, U-2003.09, September 2003.
46. R.P. Dick, D.L. Rhodes, W. Wolf, TGFF: task graphs for free, in: CODES/CASHE '98, Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 15-18 March 1998, pp. 97-101.