Throughput-Oriented NoC topology generation and analysis for high performance SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 10, 2009, Pages 1433-1446

  Dumitriu, Victor ^a   Khan, Gul N ^a  

^a RYERSON UNIVERSITY   (Canada)

Author keywords

Design automation; Network on chip (NoC); Performance analysis; System on chip (SoC)

Indexed keywords

APPLICATION-SPECIFIC; COMMUNICATION METHOD; COMPLEX SYSTEMS; DESIGN AND ANALYSIS; DESIGN AUTOMATION; DESIGN METHOD; DESIGN PROCESS; DISPLAY APPLICATION; FREQUENCY OF OPERATION; MULTI-WINDOW; NETWORK RESOURCE; NETWORK-ON-CHIP (NOC); NEW APPROACHES; ON CHIPS; ON-CHIP APPLICATIONS; PERFORMANCE ANALYSIS; PREDICTIVE ANALYSIS; REGULAR TOPOLOGY; SYSTEM-ON-CHIP (SOC); TOPOLOGY GENERATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; PREDICTIVE CONTROL SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS;

TOPOLOGY;

EID: 70349741082     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2004592     Document Type: Article

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