SAGA: Synthesis technique for guaranteed throughput NoC architectures

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 489-494

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GUARANTEED THROUGHPUTS; LARGE GRAPHS; MILP FORMULATION; MULTI-OBJECTIVE OPTIMIZATION PROBLEM; NOC ARCHITECTURES; NOVEL GENETIC ALGORITHM; OPTIMAL SOLUTIONS; RUNTIMES; SYNTHESIS TECHNIQUES;

BENCHMARKING; COMMUNICATION; COMPUTER AIDED DESIGN; ENERGY UTILIZATION; NETWORK ARCHITECTURE; TRACE ELEMENTS;

TOPOLOGY;

EID: 84861451458     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. W.J. Dally and C.L. Seitz. "Deadlock-free message routing in multiprocessor interconnection networks". IEEE Transactions on Computers, C-36(5):547-553, 1987.
4. A. Pinto, L. P. Carloni. and A. L. Sangiovanni-Vincentelli. "Efficient Synthesis of Networks On Chip". In Proceedings of ICCD, 2003.
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6. Jingcau Hu, and Radu Marculescu. "Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures". In Proceedings of DATE, 2003.
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8. N. Banerjee, P. Vellanki, and K. S. Chatha. "A Power and Performance Model for Network-on-Chip Architectures ". In Proceedings of DATE, Paris, France, February 2004.
9. K. Srinivasan, K. S. Chatha, Goran Konjevod. "Linear Programming Based Techniques for Synthesis of Network-on-Chip Architectures ". InProceedings of ICCD, October 2004.