Thermal characteristics of multi-die, three-dimensional integrated circuits with unequally sized die

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2010

Volumn , Issue , 2010, Pages

  Jain, Ankur ^a  

^a MOLECULAR IMPRINTS INC   (United States)

Author keywords

3D integrated circuits; Die stacking; Thermal modeling; Thermal electrical co design; Through silicon via (TSV)

Indexed keywords

3-D INTEGRATED CIRCUIT; CO-DESIGNS; DIE STACKING; THERMAL MODELING; THERMAL-ELECTRICAL CO-DESIGN;

DESIGN; DIES; ELECTRONICS ENGINEERING; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; HEAT SINKS; INTEGRATED CIRCUITS; OPTIMIZATION; TEMPERATURE CONTROL; THERMOANALYSIS;

THREE DIMENSIONAL;

EID: 77955177596     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2010.5501261     Document Type: Conference Paper

References (13)

1. M.B. Kleiner, S. A. Kuhn, P. Ramm, W. Weber, "Thermal analysis of vertically integrated circuits", IEDM Tech. Digest, 1995, p. 487-490.
2. T.-Y. Chiang, S.J. Souri, C.O. Chui, and K.C. Saraswat, "Thermal analysis of heterogeneous 3-D ICs with various integration scenarios", IEDM Tech. Digest, 2001, p. 681-684.
3. A. Jain, R.E. Jones, R. Chatterjee, S. Pozder, Z. Huang, "Thermal modeling and design of 3D integrated circuits", IEEE Trans Components & Packaging Tech., 33 (1), 2010.
4. B. Black, et al., "Die stacking (3D) microarchitecture", IEEE/ACM Intl Symp Microarchitecture, pp. 469-479, 2006.
5. S.M. Alam, R.E. Jones, S. Pozder, R. Chatterjee, A. Jain, "New design considerations for cost-effective three-dimensional (3D) system integration", IEEE Trans VLSI Systems, 18 (2), 2010.
6. T. Brunschwiler, H. Rothuizen, U. Kloter, H. Reichl, B. Wunderle, H. Oppermann, B. Michel, "Forced Convective Interlayer Cooling Potential in Vertically Integrated Packages", Proc. IEEE ITherm, Orlando, FL, USA, pp. 1114-1125, 2008.
7. V. Natarajan, "Convective heat transfer from a die-stacked electronic package," Proc. IEEE ITherm, Orlando, FL, USA, pp. 1132-1138, 2008.
8. B. Goplen, S.S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 86-89, 2003.
9. J. Cong, J. Wei, Y. Zhang, "A thermal-driven floorplanning algorithm for 3D ICs", Proc. IEEE/ACM Intl. Conf. Computer Aided Design, pp. 306-313, 2004.
10. A. Jain, S. Alam, S. Pozder, and R.E. Jones, "Thermal-electrical co-optimization of block-level floorplanning in 3D integrated circuits," Proc. ASME InterPACK, San Francisco, CA, USA, 2009.
11. K. Skadron, K. Sankaranarayanan, S. Velusamy, D. Tarjan, M.R. Stan, and W. Huang, "Temperature-aware microarchitecture: Modeling and implementation," ACM Trans Architecture and Code Optimization, 1(1), pp. 94-125, 2004.
12. T. Suwa, H. Hadim, "Multidisciplinary heat generating logic block placement optimization using genetic algorithm," Microelectronics J, 39 (10), pp. 1200-1208, 2008.
13. S. Pozder, R. Chatterjee, A. Jain, Z. Huang, R.E. Jones, E. Acosta, "Progress of 3D integration technologies and 3D interconnects", Proc. IEEE Intl. Interconnect Tech. Conf., 2007.