Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2010, Pages 47-54

  Hsieh, Ming Che ^a   Yu, Chih Kuang ^a   Wu, Sheng Tsai ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3DIC; FEA; Spacer; Thermal resistance; Thermal stress; TSV

Indexed keywords

3D STACKING; 3DIC; BARE DIES; CHIP STACKING; COMPUTATIONAL FLUID DYNAMICS TECHNIQUE; CONVECTION HEAT TRANSFER COEFFICIENTS; DESIGN GUIDELINES; ELECTRICAL PERFORMANCE; FINITE ELEMENT ANALYSIS MODELING; HEAT DISSIPATION; HIGHER JUNCTION TEMPERATURES; IC PACKAGE; JUNCTION TEMPERATURES; LOW-POWER CONSUMPTION; MARKET DEMAND; PACKAGING TECHNOLOGIES; PORTABLE ELECTRONICS; SYSTEM SCALING; TEMPERATURE CONCENTRATION; TEST VEHICLE; THERMAL CHARACTERISTICS; THERMAL INDUCED STRESS; THERMAL RESISTANCE; THERMAL STRESS DISTRIBUTIONS; THERMO-MECHANICAL; THERMO-MECHANICAL COUPLING; THERMOMECHANICAL COUPLING EFFECTS; THREE-DIMENSIONAL (3D); THROUGH-SILICON-VIA;

CHIP SCALE PACKAGES; COMPUTATIONAL FLUID DYNAMICS; DIES; ELECTRONICS INDUSTRY; FINITE ELEMENT METHOD; HEAT CONVECTION; SEMICONDUCTOR JUNCTIONS; STRESS CONCENTRATION; THERMAL STRESS; THERMAL VARIABLES MEASUREMENT; THERMOELASTICITY; THREE DIMENSIONAL;

PACKAGING;

EID: 77952593563     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2010.5444314     Document Type: Conference Paper

References (10)

1. Shen, Y.L., "Thermo-mechanical stresses in copper interconnects - A modeling analysis", Microelectronic Engineering, Vol. 83, pp. 446-459, 2006.
2. Vandevelde, B. et al, "Thermo-mechanics 3D-wafer level and 3D stacked IC packaging technologies", International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Mirco-Electronics and Mirco-Systems, pp. 20-26, 2008.
3. th Electronic Components and Technology Conf, 2008.
4. Kazumi, H. et al, "The Optimization of Terminal Structure for Interconnections in 3D Packaging Technology with Through-Silicon Vias", International Conference on Electronics Packaging, pp. 161-166, 2005.
5. Dong Min Jang, et al, "Development and Evaluation of 3D SiP with Vertically Interconnected Through Silicon Vias (TSV)", Electronic Components and Technology Conference, pp.847-852, 2007.
6. Hsieh, M. C. and Yu, C. K., "Thermo-mechanical simulations for 4-layer stacked IC packages", International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Mirco-Electronics and Mirco-Systems, pp. 254-260, 2008.
7. Lee, H., et al, "Thermal Characterization of High Performance MCP with Silicon Spacer Having Low Thermal Impedance", Semiconductor Thermal Measurement and Management Symposium, pp.322-326, 2005. (Pubitemid 41696295)
8. Yasuhiro Y., et al, "Thermal Characterization of Bare-die Stacked Modules with Cu through-vias", Electronic Components and Technology Conference, pp. 730-732, 2001.
9. Iannuzzelli, R., "Predicting Plated-Through-Hole Reliability in High-Temperature Manufacturing Process", Proc. of 41st Electronic Components and Technology conf., pp. 410-421, 1991.
10. th International Symposium on Advanced Packaging Materials, 2002.