Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2011, Pages 131-137

  Oprins, H ^a   Cherman, V ^a   Stucchi, M ^a   Vandevelde, B ^a   Van Der Plas, G ^a   Marchal, P ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

3D integration; thermal characterization; thermal modeling; through Si vias (TSVs)

Indexed keywords

3-D INTEGRATION; 3D STACKING; DIE PACKAGES; ELECTRONIC SYSTEMS; EXPERIMENTAL SETUP; HIGHER TEMPERATURES; HOT SPOT; INTEGRATED HEATER; INTERCONNECTION STRUCTURE; PERFORMANCE ENHANCEMENTS; STACKED DIE; STACKED DIE PACKAGES; STACKED STRUCTURE; STEADY STATE; TEMPERATURE PEAKS; TEMPERATURE PROFILES; TEST CHIPS; THERMAL BEHAVIORS; THERMAL CHARACTERIZATION; THERMAL MODEL; THERMAL MODELING; THERMAL SPREADING; THERMALLY CONDUCTIVE ADHESIVES; THROUGH-SI VIAS (TSVS); TRANSIENT THERMAL ANALYSIS;

DIES; TEMPERATURE CONTROL; THERMAL VARIABLES MEASUREMENT; THERMOANALYSIS; TRANSIENT ANALYSIS;

THREE DIMENSIONAL;

EID: 79957661092     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2011.5767190     Document Type: Conference Paper

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