A study of thermal performance for chip-in-substrate package on package

2009 European Microelectronics and Packaging Conference, EMPC 2009

Volumn , Issue , 2009, Pages

  Hung, Tuan Yu ^a   Yew, Ming Chih ^a   Chou, Chan Yen ^a   Chiang, Kuo Ning ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

3D package; CiS packaging technology; FE analysis; Thermal performance

Indexed keywords

3-D PACKAGES; FE ANALYSIS; FINITE ELEMENTS; HEAT DISSIPATION; HIGH-DENSITY; HIGH-POWER; PACKAGING TECHNOLOGIES; POWER DISSIPATION; SOLDER BUMP; THERMAL PERFORMANCE; TYPE STRUCTURES;

CHIP SCALE PACKAGES; MICROELECTRONICS; MIXED CONVECTION; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; THREE DIMENSIONAL;

PACKAGING;

EID: 70449775401     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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