Tri-level-cell phase change memory: Toward an efficient and reliable memory system

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 440-451

  Seong, Nak Hee ^a   Yeo, Sungkap ^a   Lee, Hsien Hsin S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING SYSTEM; CORRECTION MECHANISM; EMERGING MEMORY TECHNOLOGIES; INFORMATION DENSITY; PERFORMANCE IMPROVEMENTS; PHASE CHANGE MEMORY (PCM); RESISTANCE DRIFTS; SALIENT FEATURES;

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; CYTOLOGY; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; MICROPROCESSOR CHIPS;

CELLS;

EID: 84881155309     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485960     Document Type: Conference Paper

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