A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 8, 2011, Pages 1357-1367

  Xu, Wei ^a   Zhang, Tong ^b  

^a MARVELL SEMICONDUCTOR INC   (United States)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

BCH; error correction code (ECC); low density parity check (LDPC); phase change memory; resistance drift; structural relaxation

Indexed keywords

ANALYSIS AND SIMULATION; BCH; ERROR CORRECTION CODE (ECC); ERROR CORRECTION CODES; LDPC CODES; LOW-DENSITY PARITY-CHECK (LDPC); LOW-DENSITY PARITY-CHECK CODES; MEMORY CELL; MEMORY FAULT TOLERANCE; MEMORY STORAGE; PHASE CHANGES; TEST VEHICLE;

CELLS; CODING ERRORS; DATA COMMUNICATION EQUIPMENT; ERROR CORRECTION; INFORMATION THEORY; PHASE CHANGE MEMORY; SEMICONDUCTOR STORAGE; STRUCTURAL RELAXATION;

FAULT TOLERANCE;

EID: 79961002774     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2052640     Document Type: Article

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