Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration

IEEE 3D System Integration Conference 2010, 3DIC 2010

Volumn , Issue , 2010, Pages

  Reed, Jason D ^a   Goodwin, Scott ^a   Gregory, Chris ^a   Temple, Dorota ^a  

^a RTI INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ALD BARRIERS; BREAKDOWN VOLTAGE; DIRECT PLATING; ELECTRICAL PROPERTY; FILM PROPERTIES; FLAT BAND; HIGH ASPECT RATIO; MATERIAL PROPERTY; METAL INSULATORS; RELIABILITY TESTING; SEED LAYER; THERMAL OXIDE LAYER; THROUGH SILICON VIAS; TRAP DENSITY;

ATOMIC LAYER DEPOSITION; ELECTRIC PROPERTIES; ELECTRONIC EQUIPMENT TESTING; INTEGRATION; METAL INSULATOR BOUNDARIES; METAL TESTING; MIM DEVICES; MIS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES; THREE DIMENSIONAL;

ASPECT RATIO;

EID: 79955948350     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2010.5751434     Document Type: Conference Paper

References (16)

1. S. Kumar, D. Greenslit, E. Eisenbraun, "Development of Manufacturable Solutions for the Direct Plating of Copper on Robust ALD-Grown Barriers," Proc. 211th ECS Meeting, Volume 6, Issue 8, Electrochemical Processing in ULSI and MEMS, May 2007, Chicago, IL.
2. J. I. Shao, B. Baker-O'Neal, J. J. Kelly, K. Kwietniak, P. M. Vereecken, "Pretreatment of Ru liner for direct Cu plating", Proc. of 212th ECS Meeting, October 2007, Washington, DC.
3. th ECS Meeting, April 2010, Vancouver, Canada.
4. C. Truzzi, F. Raynal, V. Mevellec, "Wet-Process Deposition of TSV Liner and Metal Films", Proc. of 2009 3DIC Conference, September 2009, San Francisco.
5. th ECTC, June 2010, Las Vegas, NV.
6. D. R. Lide, W. M. Haynes, "CRC Handbook of Chemistry and Physics, 2009-2010, 90th ed.", CRC Press, Boca Raton, FL 2009.
7. M. W. Lane, C. E. Murray, F. R. McFeely, P. M. Vereecken, R. Rosenberg, "Liner materials for direct electrodeposition of Cu", Appl. Phys. Lett. Vol. 83, No. 12, pp 2330-2332, 2003.
8. th ECS Meeting, Honolulu, Oct 2008.
9. P. Solomon, "Breakdown in Silicon Oxide - A Review", Journal of Vacuum Science and Technology, vol. 14, pp. 1122-1130, Sept. 1977.
10. G.D. Wilk, R. M. Wallace, J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations." J. Appl. Phys. Applied Physics Review, Vol. 89, number 9, p. 5243, 2001.
11. J. Robertson, "High dielectric constant gate oxides for metal oxide Si transistors" Reports on Progress in Physics Vol. 69, No. 2, 327, 2006.
12. nd Ed., Wiley-Interscience, New York, pp. 362-397, September 1981.
13. J. Kolodzey, E. A. Chowdhury, T. N. Adam, G. Qui, I. Rau, J. O. Olowolafe, J. S. Suehle, Y. Chen, "Electrical Conduction and Dielectric Breakdown in Aluminum Oxide Insulators on Silicon", IEEE Trans. Electron Devices, Vol. 47, No. 1, pp 121-128, Jan 2000.
14. E.H Nicollian, J.R. Brews, "MOS Physics and Technology", Wiley-Interscience, New York, 1982.
15. H.Y. Yu, J.F. Kang, J.D. Chen, C. Ren, Y.T. Hou, S.J. Whang, M.-F. Li, D.S.H. Chan, K.L. Bera, C.H. Tung, A. Du, D.-L. Kwong, "Thermally Robust High Quality HfN/HfO2 Gate Stack for Advanced CMOS Devices" International Electron Device Meeting , Washington DC, December 2003, pp. 99-102.
16. J. D. Oliver, H. C. Cramer, and R. J. Porter, "Layout Design Rule Effects on Capacitor Reliability", CS MANTECH Conference, April 14-17, 2008, Chicago, Illinois.