Conformal low -temperature dielectric deposition process below 200°C for TSV application

2010 12th Electronics Packaging Technology Conference, EPTC 2010

Volumn , Issue , 2010, Pages 27-30

  Praveen, Sampath Kumar ^a   Tsan, Ho Wai ^a   Nagarajan, Ranganathan ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMAL DEPOSITION; DIELECTRIC DEPOSITION; HIGH ASPECT RATIO; LOW TEMPERATURES; MECHANICAL STRESS; OPTIMAL CONDITIONS; OXIDE DEPOSITION; OXIDE STRESS; PRESSURE AND TEMPERATURE; STEP COVERAGE;

ELECTRONICS PACKAGING; STRESSES;

ASPECT RATIO;

EID: 79951932248     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702600     Document Type: Conference Paper

References (6)

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3. Keoth Buchanan et al, 'Etch Dielectrics and metal barrier-Seed fpr low temperature TSV processing 3D System Integration, 2009. 3DIC 2009. IEEE
4. D. Archard et al, 'Low temperature PECVD of Dielectric Films for TSV Applications', Electronic Components and Technology Co,2010.Pp764-768
5. J.J. Hsieh et al, VMIC Conf. 1989, pp. 411-415
6. Ch. Voulgaris et al,'RF power effect on TEOS/O2 PECVD of silicon oxide thin films' Surface & Coating Technology 200(2005) 351-354.