Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1166-1172

  Xie, B ^a   Shi, X Q ^a   Chung, C H ^a   Lee, S W R ^b  

^a HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE   (Hong Kong)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-LEVEL; COEFFICIENT OF THERMAL EXPANSION; GLOBAL-LOCAL; INTERCONNECTION TECHNOLOGY; LEVEL MODEL; LOW COSTS; MANUFACTURING PROCESS; NONUNIFORMITY; PLATING PROCESS; PLATING SOLUTIONS; PROCESS PARAMETERS; SEED THICKNESS; SIMULATION METHODOLOGY; SIMULATION METHODS; SIMULATION PROCEDURES; THERMO-MECHANICAL ANALYSIS; THERMOMECHANICAL SIMULATION; THROUGH-SILICON-VIA; WAFER EDGE; WAFER LEVEL;

PLATING; SILICON WAFERS; THERMAL EXPANSION; THERMOMECHANICAL TREATMENT;

COMPUTER SIMULATION;

EID: 77955193255     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490849     Document Type: Conference Paper

References (10)

1. Chang, H. H., et al., "3D Stacked Chip Technology Using Bottom-Up Electroplated TSVs", Electronic Components and Technology Conference (2009), pp. 1177-1184.
2. Ramm, P., et al., "Through Silicon Via Technology - Processes and Reliability for Wafer-Level 3D System Integration", Electronic Components and Technology Conference (2008), pp. 841-846.
3. Tezcan, Deniz Sabuncuoglu, et al., "Sloped Through Wafer Vias for 3D Wafer Level Packaging", Electronic Components and Technology Conference (2007), pp. 643-647.
4. Tezcan, Deniz Sabuncuoglu, et al., "Scalable Through Silicon Via with Polymer Deep Trench Isolation for 3D Wafer Level Packaging", Electronic Components and Technology Conference (2009), pp. 1159-1164.
5. Lu, Kuan H., et al., "Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias", Electronic Components and Technology Conference (2009), pp. 630-634.
6. Chen, Zhaohui, et al., "Thermo-Mechanical Characterization of Copper Filled and Polymer Filled TSVs Considering Nonlinear Material Behaviors", Electronic Components and Technology Conference (2009), pp. 1374-1380.
7. Wunderle, B., et al., "Simulation of Thermo-Mechanical Reliability of Through Silicon Vias", International Workship on 3D System Integration, Munich, Germany, Oct. 2007.
8. Ramm, P., et al., "Through Silicon Via Technology-Processes and Reliability for Wafer-Level 3D System Integration", Electronic Components and Technology Conference (2008), pp. 841-846.
9. Selvanayagam, Cheryl S., et al., "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV and their Flip-Chip Microbumps", Electronic Components and Technology Conference (2008), pp. 1073-1081.
10. 10.Liu, Xi, et al., "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon-Vias", Electronic Components and Technology Conference (2009), pp. 624-629.