Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 53-55

  Teh, W H ^a,b   Caramto, R ^a,c   Arkalgud, S ^a   Saito, T ^d   Maruyama, K ^d   Maekawa, K ^e  

^a SEMATECH   (United States)

^b INTEL CORPORATION   (United States)

^c SUNY POLYTECHNIC INSTITUTE   (United States)

^d TOKYO ELECTRON LTD   (Japan)

^e TEL TECHNOLOGY CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 300 MM WAFERS; BOWING EFFECT; COUPLED PLASMA; ETCH PROCESS; ETCH RATES; ETCHING CHARACTERISTICS; ETCHING SYSTEMS; KEY FACTORS; LOGIC INTEGRATION; NOMINAL FEATURE; SIDEWALL ROUGHNESS; THROUGH SILICON VIAS;

INDUCTIVELY COUPLED PLASMA; PLASMA ETCHING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TANTALUM; TANTALUM COMPOUNDS; THREE DIMENSIONAL;

ANISOTROPIC ETCHING;

EID: 70349463107     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090338     Document Type: Conference Paper

References (5)

1. 2007 ITRS Roadmap- Interconnect Emerging Technologies Section
2. B. Swinnen et. al., "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias," IEDM 2006
3. P.S. Andry et. al., "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications," IBM J. Res. Dev. 52(6), p. 571, 2008
4. P. Ramm and A. Klumpp, "Through-Silicon Via Technologies for Extreme Miniaturized 3D Integrated Wireless Sensor Systems (e-CUBES)," IITC 2008, p. 7
5. 2 interconnection system to plastic substrates," IEEE Elec. Dev. Lett. 26(11), p. 802, 2005