Power-performance co-optimization of throughput core architecture using resistive memory

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 342-353

  Goswami, Nilanjan ^a   Cao, Bingyi ^a   Li, Tao ^a  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MASSIVELY PARALLEL COMPUTING; PERFORMANCE DEGRADATION; PERFORMANCE IMPROVEMENTS; REGISTER FILE ORGANIZATIONS; SCRATCH PAD MEMORY; SPIN TRANSFER TORQUE; UPDATE MECHANISMS; WRITE OPERATIONS;

COST REDUCTION; DYNAMIC RANDOM ACCESS STORAGE; DYNAMICS; MEMORY ARCHITECTURE; MRAM DEVICES; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; STATIC RANDOM ACCESS STORAGE; SUPERCOMPUTERS; THROUGHPUT;

CACHE MEMORY;

EID: 84880269380     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522331     Document Type: Conference Paper

References (46)

1. NVIDIA Corporation, "NVIDIA's Next Generation CUDA Compute Architecture: Fermi", Nvidia White Paper, 2009.
2. N. Brookwood, "AMD Fusion Family of APUs: Enabling a Superior, Immersive PC Experience", AMD White Paper, 2010.
3. S. Hong and H. Kim, "An Integrated GPU Power and Performance Model", ISCA, 2010.
4. M. Gebhart, D. Johnson, D. Tarjan, S. Keckler, W. Dally, E. Lindholm, and K. Skadron, "Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors", ISCA, 2011.
5. A. Maashri, G. Sun, X. Dong, V. Narayanan and Y. Xie, "3D GPU Architecture Using Cache Stacking: Performance, Cost, Power and Thermal Analysis", ICCD, 2009.
6. H. Nagasaka, N. Maruyama, A. Nukada, T. Endo, and S. Matsuoka, "Statistical Power Modeling of GPU Kernels using Performance Counters", ICGC, 2010.
7. U.R.D. International, Inc. DC Current Sensor Model: HCS-20-10-AP.
8. A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, "Analyzing CUDA Workloads Using a Detailed GPU Simulator", ISPASS, 2009.
9. C. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. Stan, "Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches", HPCA, 2011.
10. X. Guo, E. Ipek, and T. Soyata, "Resistive Computation: Avoiding the Power Wall with Low-Leakage, STT-MRAM based Computing", SIGARCH Comput. Archit. News, vol. 38, no. 3, pp. 371-382, 2010.
11. "International Technology Roadmap for Semiconductors," ITRS, 2009.
12. E. Technologies, "Everspin Debuts First Spin-Torque MRAM for High Performance Storage Systems ", 2012. http://www.everspin.com/PDF/ST-MRAM- Press-Release.pdf.
13. X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement", DAC, 2008.
14. S. Lai and T. Lowrey, "OUM-A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications", IEDM, 2001.
15. F. Tabrizi, "The Future of Scalable STT-RAM as a Universal Embedded Memory", EETimes Design, 2007. http://www.eetimes.com/design/embedded/ 4026000/The-future-ofscalable-STT-RAM-as-A-universal-embedded-memory.
16. C. Smullen, A. Nigam, S. Gurumurthi, and M.R. Stan, "The STeTSiMS STT-RAM Simulation and Modeling System", ICCAD, 2011.
17. A. Mishra, X. Dong, G. Sun, Y. Xie, N. Vijaykrishnan, and C. Das, "Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs", ISCA, 2011.
18. S. Li, J. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi, "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures", MICRO, 2009.
19. R. Buhrman, "Spin Torque MRAM-Challenges and Prospects", DRC, 2009.
20. Y. Chen, X. Wang, H. Li, H. Xi, Y. Xie, and W. Zhu, "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 12, pp. 1724-1734, 2010.
21. S. Liu, J. Lindholm, M. Siu, B. Coon, and S. Oberman, "Operand Collector Architecture", U.S. Patent 7834881, 2010.
22. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "Energy Reduction for STT-RAM Using Early Write Termination", ICCAD, 2009.
23. S. Ranganathan, "High Performance Architecture for a Writeback Stage", U.S. Patent 7519794, 2009.
24. S. Thoziyoor, N. Muralimanohar, J. Ahn, and N. Jouppi, "CACTI 6.5", hpl.hp.com. http://www.hpl.hp.com/research/cacti.
25. Denali Software, Inc., "Using Configurable Memory Controller Design IP with Encounter RTL Complier", Cadence CDNLive, 2007.
26. NVIDIA Corporation, "GPU Computing SDK", developer.nvidia.com, 2010. http://developer.nvidia.com/gpucomputing-sdk.
27. Impact Research Group, "Parboil Benchmark Suite", impact.crhc.illinois.edu, 2010. http://impact.crhc.illinois.edu/parboil.php.
28. S. Che, M. Boyer, J. Meng, D. Tarjan, J. Sheaffer, S. Lee, and K. Skadron, "Rodinia: A Benchmark Suite for Heterogeneous Computing", IISWC, 2009.
29. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, "New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation", CICC, 2000.
30. G. Sun, X. Dong, Y, Xie, J. Li, and Y. Chen, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs", HPCA, 2009.
31. M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, H. Nagao, and H. Kano, "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-Ram", IEDM, 2005.
32. S. Lee, H. Lee, S. Kim, S. Lee, and H. Shin, "A Novel Macro-Model for Spin-Transfer-Torque based Magnetic-Tunnel-Junction Elements", Solid-State Electronics, vol. 54, no. 4, pp. 497-503, 2010.
33. NVIDIA Corporation, "NVIDIA CUDA Programming Guide".
34. J. Nickolls, I. Buck, M. Garland, and K. Skadron, "Scalable Parallel Programming with CUDA", ACM Queue, vol. 6, no. 2, pp. 40-53, 2008.
35. W. Zhao, E. Belhaire, Q. Mistral, E. Nicolle, T. Devolder, and C. Chappert, "Integration of Spin-RAM Technology in FPGA Circuits", ICSICT, 2006.
36. W. Zhao, E. Belhaire, C. Chappert, F. Jacquet, and P. Mazoyer, "New Non-volatile Logic based on Spin-MTJ", Physica Status Solidi (a), vol. 205, no. 6, pp. 1373-1377, 2008.
37. X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, "Hybrid Cache Architecture with Disparate Memory Technologies", ISCA, 2009.
38. M. Franklin and G.S. Sohi, "Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors", SIGMICRO Newsletter, vol. 23, no. 1, pp. 236-245, 1992.
39. R. Balasubramonian, S. Dwarkadas, and D. Albonesi, "Reducing the Complexity of the Register File in Dynamic Superscalar Processors", MICRO, 2001.
40. E. Borch, S. Manne, J. Emer, and E. Tune, "Loose Loops Sink Chips", HPCA, 2002.
41. T. Jones, M. O'Boyle, J. Abella, A. Gonzalez, and O. Ergin, "Energy-Efficient Register Caching with Compiler Assistance", ACM Trans. Archit. Code Optim., vol. 6, no. 4, pp. 1-23, 2009.
42. J. Cruz, A. Gonzalez, M. Valero, and N. Topham, "Multiple-Banked Register File Architectures", SIGARCH Comput. Archit. News, vol. 28, no. 2, pp. 316-325, 2000.
43. P. Nuth and W. Dally, "The Named-State Register File: Implementation and Performance", HPCA, 1995.
44. H. Zeng and K. Ghose, "Register File Caching for Energy Efficiency", ISLPED, 2006.
45. P. Satyamoorthy, "STT-RAM for Shared Memory in GPUs", M.S. Thesis, School of Engineering and Applied Science, University of Virginia, 2011.
46. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A Durable and Energy Efficient Main Memory using Phase Change Memory Technology", ISCA, 2009.