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Volumn , Issue , 2009, Pages 254-259

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis

Author keywords

[No Author keywords available]

Indexed keywords

3D TECHNOLOGY; COMMUNICATION BANDWIDTH; CYCLE TIME; GEOMETRIC MEAN; GRAPHICS PROCESSING UNITS; PROCESSING POWER; STACKING TECHNOLOGY; THERMAL ANALYSIS;

EID: 77951019767     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413147     Document Type: Conference Paper
Times cited : (33)

References (23)
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    • Nvidia: CUDA Homepage
  • 4
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    • Understanding the efficiency of GPU algorithms for Matrix-Matrix multiplication
    • K. Fatahalian, J. Sugerman, and P. Hanrahan, "Understanding the Efficiency of GPU Algorithms for Matrix-Matrix Multiplication," in Proc. SIGGRAPH, 2004, pages 133-137
    • (2004) Proc. SIGGRAPH , pp. 133-137
    • Fatahalian, K.1    Sugerman, J.2    Hanrahan, P.3
  • 6
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    • Cache and bandwidth aware matrix multiplication on the GPU
    • University of Illinois Urbana-Champain
    • J. D. Hall, N. Carr, and J. Hart, "Cache and Bandwidth Aware Matrix Multiplication on the GPU," Technical Report UIUCDCS-R-2003-2328, University of Illinois Urbana-Champain.
    • Technical Report UIUCDCS-R-2003-2328
    • Hall, J.D.1    Carr, N.2    Hart, J.3
  • 9
    • 34547673128 scopus 로고    scopus 로고
    • Thermal herding: Microarchitecture techniques for controlling hotspots in High-Performance 3D-Integrated processors
    • K. Puttaswamy, G. H. Loh, "Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors," in Proc. HPCA, 2007, pp 193-204.
    • (2007) Proc. HPCA , pp. 193-204
    • Puttaswamy, K.1    Loh, G.H.2
  • 13
    • 77950990849 scopus 로고    scopus 로고
    • 2008 IC economics report
    • S. Jones, "2008 IC Economics Report," In IC Knowledge LLC, 2008.
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    • Jones, S.1
  • 14
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    • IP gate count estimation methodology during microarchitecture phase
    • V. K. Kodavalla, "IP Gate Count Estimation Methodology during MicroArchitecture Phase," in IP based Electronic System, 2007
    • (2007) IP Based Electronic System
    • Kodavalla, V.K.1
  • 18
    • 33847743417 scopus 로고    scopus 로고
    • A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram
    • M. Hosomi, H. Yamagishi, and T. Yamamoto, "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram," in Inter-national Electron Devices Meeting, 2005, pages 459-462
    • (2005) Inter-national Electron Devices Meeting , pp. 459-462
    • Hosomi, M.1    Yamagishi, H.2    Yamamoto, T.3
  • 19
    • 77951008573 scopus 로고    scopus 로고
    • Attila Project: AttilaWiki, available online: https://atti.la.ac.upc.edu/ wiki/index.php/Main-Page, 2008
    • (2008) Attila Project: AttilaWiki
  • 20
    • 77950984619 scopus 로고    scopus 로고
    • GeForce 9400 GT Specifications, available online: http://www.nvidia.com/ object/product-geforce-9400gt-us.html
    • GeForce 9400 GT Specifications
  • 23
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    • Real-Time graphics architecture
    • Stanford University
    • -(Online Course Resource) K. Akeley, and P. Hanrahan, "Real-Time Graphics Architecture," CS448 Spring 2007, Stanford University
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    • Akeley, K.1    Hanrahan, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.