Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 12, 2010, Pages 1724-1734

  Chen, Yiran ^a   Wang, Xiaobin ^a   Li, Hai ^b   Xi, Haiwen ^a   Yan, Yuan ^c   Zhu, Wenzhong ^a  

^a SEAGATE TECHNOLOGY   (United States)

^b POLYTECHNIC UNIVERSITY   (United States)

^c SAN JOSE RESEARCH CENTER   (United States)

Author keywords

Magnetic devices; magnetic memories; spin transfer torque (STT)

Indexed keywords

CELL DESIGN; CELL MODEL; CMOS TECHNOLOGY; DESIGN MARGIN; DYNAMIC DESIGN; ELECTRIC LEVELS; ELECTRICAL RESPONSE; MAGNETIC MEMORIES; MAGNETIC TUNNELING JUNCTIONS; MEMORY CELL; MOS TRANSISTORS; RANDOM ACCESS MEMORIES; SCALED TECHNOLOGIES; SPIN TRANSFER TORQUE; SWITCHING CURRENTS; TECHNOLOGY NODES; THERMAL STABILITY; WRITE OPERATIONS;

CMOS INTEGRATED CIRCUITS; DESIGN; MAGNETIC STORAGE; MAGNETISM; NANOTECHNOLOGY; TECHNOLOGY; THERMODYNAMIC STABILITY; TORQUE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

RANDOM ACCESS STORAGE;

EID: 78649521473     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2032192     Document Type: Article

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