Nanoscale channel engineered double gate MOSFET for mixed signal applications using high-k dielectric

International Journal of Circuit Theory and Applications

Volumn 41, Issue 6, 2013, Pages 608-618

  Nirmal, D ^a   Vijayakumar, P ^b   Shruti, K ^a   Mohankumar, N ^c  

^a KARUNYA UNIVERSITY   (India)

^b KARPAGAM COLLEGE OF ENGINEERING   (India)

^c SKP Engineering Collage   (India)

Author keywords

carrier transport efficiency; dielectric materials; equivalent oxide thickness (EOT); FinFET; lateral asymmetric channel; threshold voltage roll off

Indexed keywords

CARRIER TRANSPORT EFFICIENCY; EQUIVALENT OXIDE THICKNESS; FINFET; LATERAL ASYMMETRIC CHANNEL; THRESHOLD VOLTAGE ROLL-OFF;

ELECTRIC NETWORK ANALYSIS; GATE DIELECTRICS; INTEGRATED CIRCUITS; MOS DEVICES; MOSFET DEVICES; NANOTECHNOLOGY; SILICA; THRESHOLD VOLTAGE;

DIELECTRIC MATERIALS;

EID: 84879410222     PISSN: 00989886     EISSN: 1097007X     Source Type: Journal    
DOI: 10.1002/cta.1800     Document Type: Article

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