메뉴 건너뛰기




Volumn 54, Issue 2, 2007, Pages 241-248

Impact of halo doping on the subthreshold performance of deep-submicrometer CMOS devices and circuits for ultralow power analog/ mixed-signal applications

Author keywords

CMOS; Halo; Lateral asymmetric channel (LAC); Mixed signal; Subthreshold; Ultralow power

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG CIRCUITS; DOPING (ADDITIVES); GAIN MEASUREMENT;

EID: 33847645306     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.888630     Document Type: Article
Times cited : (88)

References (16)
  • 2
    • 0036712433 scopus 로고    scopus 로고
    • "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications"
    • Sep
    • H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1558-1565, Sep. 2002.
    • (2002) IEEE Trans. Electron Devices , vol.49 , Issue.9 , pp. 1558-1565
    • Deshpande, H.V.1    Cheng, B.2    Woo, J.C.S.3
  • 3
    • 0346707543 scopus 로고    scopus 로고
    • "Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance"
    • Dec
    • K. Narasimhulu, D. K. Sharma, and V. R. Rao, "Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2481-2489, Dec. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.12 , pp. 2481-2489
    • Narasimhulu, K.1    Sharma, D.K.2    Rao, V.R.3
  • 4
    • 0035691874 scopus 로고    scopus 로고
    • "Analog device design for low power mixed mode application in deep submicron CMOS technology"
    • Dec
    • H. V. Despande, B. Cheng, and J. C. S. Woo, "Analog device design for low power mixed mode application in deep submicron CMOS technology," IEEE Electron Device Lett., vol. 22, no. 12, pp. 588-590, Dec. 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , Issue.12 , pp. 588-590
    • Despande, H.V.1    Cheng, B.2    Woo, J.C.S.3
  • 5
    • 0032650119 scopus 로고    scopus 로고
    • "An 0.1-μm asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability"
    • Apr
    • H. Shin and S. Lee, "An 0.1-μm asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability," IEEE Trans. Electron Devices, vol. 46, no. 4, pp. 820-822, Apr. 1999.
    • (1999) IEEE Trans. Electron Devices , vol.46 , Issue.4 , pp. 820-822
    • Shin, H.1    Lee, S.2
  • 6
    • 0033334509 scopus 로고    scopus 로고
    • "Exploration of velocity overshoot in a high-performance deep sub-0.1 μm SOI MOSFET with asymmetric channel profile"
    • Oct
    • B. Cheng, V. R. Rao, and J. C. S. Woo, "Exploration of velocity overshoot in a high-performance deep sub-0.1 μm SOI MOSFET with asymmetric channel profile," IEEE Electron Device Lett., vol. 20, no. 10, pp. 538-540, Oct. 1999.
    • (1999) IEEE Electron Device Lett. , vol.20 , Issue.10 , pp. 538-540
    • Cheng, B.1    Rao, V.R.2    Woo, J.C.S.3
  • 8
    • 4444331816 scopus 로고    scopus 로고
    • "The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance"
    • Sep
    • K. Narasimhulu, M. P. Desai, S. G. Narendra, and V. R. Rao, "The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1416-1423, Sep. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.9 , pp. 1416-1423
    • Narasimhulu, K.1    Desai, M.P.2    Narendra, S.G.3    Rao, V.R.4
  • 10
    • 13344280331 scopus 로고    scopus 로고
    • "Device optimization for digital subthreshold logic operation"
    • Feb
    • B. C. Paul, A. Raychowdhury, and K. Roy, "Device optimization for digital subthreshold logic operation," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 237-247, Feb. 2005.
    • (2005) IEEE Trans. Electron Devices , vol.52 , Issue.2 , pp. 237-247
    • Paul, B.C.1    Raychowdhury, A.2    Roy, K.3
  • 11
    • 0017503796 scopus 로고
    • "CMOS analog integrated circuits based on weak inversion operation"
    • Jun
    • E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operation," IEEE J. Solid-State Circuits, vol. SSC-12, no. 3, pp. 224-231, Jun. 1977.
    • (1977) IEEE J. Solid-State Circuits , vol.SSC-12 , Issue.3 , pp. 224-231
    • Vittoz, E.1    Fellrath, J.2
  • 12
    • 0018046826 scopus 로고
    • "Design of integrated analog CMOS circuits - A multichannel telemetry transmitter"
    • Dec
    • W. Steinhagen and W. L. Engl, "Design of integrated analog CMOS circuits - A multichannel telemetry transmitter," IEEE J. Solid-State Circuits, vol. SSC-13, no. 6, pp. 799-805, Dec. 1978.
    • (1978) IEEE J. Solid-State Circuits , vol.SSC-13 , Issue.6 , pp. 799-805
    • Steinhagen, W.1    Engl, W.L.2
  • 14
    • 33847651579 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors
    • International Technology Roadmap for Semiconductors, 2001.
    • (2001)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.