Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

Microelectronics Journal

Volumn 35, Issue 9, 2004, Pages 761-765

  Reddy, G Venkateshwar ^a   Kumar, M Jagadesh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Channel engineering; Double Gate (DG) SOI MOSFET; Silicon on insulator (SOI); Single halo (SH)

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; LEAKAGE CURRENTS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

CHANNEL ENGINEERING; DRAIN VOLTAGE; SINGLE HALO (SH);

MOSFET DEVICES;

EID: 3943112926     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2004.06.003     Document Type: Article

References (18)

1. Chaudhry A., Kumar M.J. Controlling short-channel effects in deep submicron SOI MOSFETS for improved reliability: a review. IEEE Trans. Dev. Mater. Reliab. 4:(3):2004;99-109.
2. Frank D.J., Dennard R.H., Nowak E., Solomon D.M., Taur Y., Wong H. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE. 89:(3):2001;259-288.
3. Horie H., Ando S., Tanaka T., Imai M., Arimoto Y., Hijiya S. Fabrication of double-gate thin-film SOI MOSFETs using wafer bonding and polishing. SSDM. 1991;165-167.
4. + double-gate thin film SOI MOSFET's. IEDM. 1991;683-686.
5. Venkatesan S., Neudeck G.W., Pierret R.F. Dual gate operation and volume inversion in n-channel SOI MOSFET's. IEEE Electron Dev. Lett. 13:(1):1992;44-46.
6. Suzuki K., Tosaka Y., Tanaka T., Horie H., Arimoto Y. Scaling theory of double-gate SOI MOSFET's. IEEE Trans. Electron Dev. 40:(12):1993;2326-2329.
7. Tosaka T., Suzuki K., Horie H., Sugii T. Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's. IEEE Electron Dev. Lett. 15:(11):1994;466-468.
8. Codella C.F., Ogura S. Halo doping effects in submicron DI-LDD device design. IEDM. 1985;230-231.
9. Hori T. A 0.1-μm CMOS technology with tilt-implanted punchthrough stopper (TIPS). IEDM. 1994;75-78.
10. Odanaka S., Hiroki, A. Potential design and transport property of 0.1 μm MOSFET with asymmetric channel profile. IEEE Trans. Electron Dev. 44:(4):1997;595-600.
11. Cheng B., Ramgopal Rao V., Woo J.C.S. Sub 0.18 μm SOI MOSFETs using lateral symmetric channel profile and Ge pre-amorphization salicide technology. Proc. IEEE. 18:1998;113-114.
12. MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, 1997.
13. Zhou X., Lim K.Y., Lim D. A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling. IEEE Trans. Electron Dev. 46:(4):1999;807-809.
14. Kumar M.J., Chaudhry A. Two-dimensional analytical modeling of fully depleted dual-material gate (DMG) SOI MOSFET and evidence for diminished short-channel effects. IEEE Trans. Electron Dev. 51:(4):2004;569-574.
15. Hanafi H.I., Noble W.P., Bass R.S., Varahramyan K., Lii Y., Dally A.J. A model for anomalous short-channel behavior in submicron MOSFET's. IEEE Electron Dev. Lett. 14:(12):1993;575-577.
16. Tanaka J., Toyabe T., Matsuo H., Ihara S., Masuda H., Otsuka F. Reverse short-channel effect of threshold voltage in LOCOS parasitic MOSFET's. Solid State Electron. 38:(3):1995;567-572.
17. Hsu S.T., Kalish I.H., Suzuki K., Kawabata R., Shibayama H. Physical mechanism of the reverse short-channel effect in MOS transistors. Solid State Electron. 34:(6):1991;605-608.
18. Arora N.D., Sharma M.S. Modeling the anomalous threshold voltage behavior of submicrometer MOSFET's. IEEE Electron Dev. Lett. 13:(2):1992;92-94.